mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00

History

Rose Thompson 9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.		2024-07-19 17:08:47 -05:00
..
Makefile	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
README.md	Update README and put logs in the right places.	2024-04-11 20:16:55 -07:00
sim-wally-batch	ignore VCS junk files	2024-04-21 19:49:55 -07:00
wrapper.c	Add support for getenvval as wrapper for Verilator's getenv.	2024-04-12 14:59:04 -07:00

README.md

Simulation with Verilator

Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with +TEST=<testsuite>.

Demand:

Avoid unnecessary compilation by sharing the same executable for a specific configuration
- executables are stored in obj_dir_non_profiling and obj_dir_profiling correspondingly
Wsim should support -s verilator option and run simulation with Verilator.

Folder Structure

This folder contains the following files that help the simulation of Wally with Verilator:

Makefile: simplify the usage with Verialtor
executables
- obj_dir_non_profiling: non-profiling executables for different configurations
- obj_dir_profiling: profiling executables for different configurations
logs in logs and logs_profiling correspondingly
[NOT WORKING] logs: contains all the logs

Examples

# non-profiling mode
make WALLYCONF=rv64gc TEST=arch64i run
# profiling mode
make WALLYCONF=rv64gc TEST=arch64i profile

# remove all the temporary files, including executables and logs
make clean