Ross Thompson
0b06fa12ef
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
16aa3127b6
Merge branch 'testDivInterruptInterlock' of github.com:davidharrishmc/riscv-wally into testDivInterruptInterlock
2022-01-12 14:17:49 -06:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d
Hack "fix" to prevent interrupt from occuring during an integer divide.
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This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
ecd3912900
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
2ed052f152
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
87485f9f64
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
David Harris
e41ce09b5d
C sum example
2022-01-12 09:04:41 +00:00
James E. Stine
52a8ac9132
remove extraneous
2022-01-11 16:01:48 -06:00
James E. Stine
63a37395ef
Update on assembly simple/spike
2022-01-11 15:59:56 -06:00
David Harris
c0439110e9
Added inline assembly to simple
2022-01-11 21:32:30 +00:00
David Harris
b1a780e677
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-11 21:01:50 +00:00
David Harris
e25760d8e5
Added C test cases
2022-01-11 21:01:48 +00:00
Kip Macsai-Goren
c99456d5e7
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
David Harris
2a7e77d2b1
Do file for riscvsingle
2022-01-10 16:26:18 +00:00
David Harris
6587bd6944
Added fulladder example files
2022-01-10 16:15:05 +00:00
David Harris
4cae11ad28
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
50c17f2a03
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
467aac8463
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
55456e465c
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
e01c8bc5f6
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
3109fa1383
Fixed wavefile.
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Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
Ross Thompson
73f7d36529
Added additional fsm to ILA.
2022-01-09 17:10:57 -06:00
Ross Thompson
c8689dc6ce
Possible fix for the TrapM DTLBMiss suppression.
2022-01-09 14:22:14 -06:00
Kip Macsai-Goren
53f3a6dbab
comment cleanup
2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
9412a5ff2d
updated PMA tests, everything passes except successful writes to protected regions.
2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
a22dc4d163
changed test case types to lookup table instead of beq's
2022-01-09 16:56:37 +00:00
David Harris
89ee6c778e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
David Harris
80c87d16a9
Fixed RISCV path in coremark Makefile
2022-01-09 14:39:22 +00:00
Ross Thompson
2846118261
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-08 20:49:45 -06:00
Ross Thompson
b856301ecf
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-08 17:21:27 -06:00
Ross Thompson
9c3dffb714
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-08 14:21:58 -06:00
Ross Thompson
09d605ac6a
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
88d5edaf13
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
Ross Thompson
b6ae6fea27
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
453a794f86
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
913a78323c
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
6c0cd5ef20
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
8481c93e1b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
de3bbd3fe0
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
