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Configurable RISC-V Processor
b6ae6fea27
only at the start of a request. Pending interrupt was used to start one of these suppressions; however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an interrupt becam pending then the the next request (eviction) made by the cache was also suppressed. This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request to the bus fsm, but the pending interrupt ignored the request. The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt it is better to use interrupt which will be disabled if the dcache is currently processing the evict. |
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| addins | ||
| benchmarks/riscv-coremark | ||
| bin | ||
| examples | ||
| fpga | ||
| pipelined | ||
| tests | ||
| .gitattributes | ||
| .gitignore | ||
| .gitmodules | ||
| LICENSE | ||
| Makefile | ||
| README.md | ||
| setup.sh | ||
| wallyVirtIO.patch | ||
riscv-wally
Configurable RISC-V Processor
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
See Chapter 2 of draft book of how to install and compile tests.