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Configurable RISC-V Processor
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Ross Thompson 9c3dffb714 Hack "fix" to prevent interrupt from occuring during an integer divide. 
This is not the desired solution but will allow continued debuging of linux.
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pipelined Hack "fix" to prevent interrupt from occuring during an integer divide. 2022-01-08 14:21:58 -06:00
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README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.