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Author	SHA1	Message	Date
David Harris	f91c1aa3ea	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-08 16:41:13 +00:00
David Harris	9ad3f26365	Restored E tests to makefrag	2022-02-08 16:41:11 +00:00
bbracker	9cb94d18b3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-08 16:08:04 +00:00
David Harris	e5097e67d4	Fixed TIM tests; rv32e test still failing	2022-02-08 15:24:37 +00:00
David Harris	e9a519a228	Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail	2022-02-08 12:40:02 +00:00
David Harris	096242a6d8	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
bbracker	61f2ae929b	update buildroot main.config to reflect most recent image build	2022-02-08 11:47:26 +00:00
bbracker	9ee4b39b01	restore trace generation functionality for new setup	2022-02-08 11:45:42 +00:00
bbracker	f642e4fb2c	gitignore dtb's because we only care about dts's as being source files	2022-02-08 11:14:59 +00:00
bbracker	b165fe3937	add trimmed-down virt devicetree to repo for QEMU	2022-02-08 11:11:44 +00:00
David Harris	f31e4910a8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-08 10:26:39 +00:00
David Harris	72c2166223	Lab 3 file cleanup	2022-02-08 10:26:37 +00:00
bbracker	775e07d69a	trying to move away from QEMU patches	2022-02-08 10:05:38 +00:00
bbracker	26f2c139e6	fix typo	2022-02-08 08:12:45 +00:00
bbracker	8688c457cb	add buildroot script	2022-02-08 08:10:32 +00:00
bbracker	929a9f0f1d	refactor buildroot-config-src into linux folder	2022-02-08 00:26:06 +00:00
bbracker	3263f5da77	trim away unneeded linker and header files intended for non-spike machines from wally-riscv-arch-test	2022-02-07 23:59:47 +00:00
David Harris	60c3cdad3a	Reverted cache change	2022-02-07 14:47:20 +00:00
David Harris	d0c40cca7a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-07 14:43:31 +00:00
David Harris	c21eb67a07	Cache syntax cleanup	2022-02-07 14:43:24 +00:00
Kip Macsai-Goren	2ef5f2612f	fixed verify step to work correctly with comments. clarified copy references without simulating	2022-02-06 19:48:23 +00:00
Kip Macsai-Goren	38b75e85a0	added new tests to make and testbench	2022-02-06 19:47:22 +00:00
Kip Macsai-Goren	5377dde581	clarified csr write test	2022-02-06 19:46:29 +00:00
Kip Macsai-Goren	6e3bec9aa5	added CSR permission tests	2022-02-06 19:45:58 +00:00
Kip Macsai-Goren	04197273f6	light cleanup	2022-02-06 02:05:59 +00:00
Kip Macsai-Goren	c5b6f49b2f	added comments to existing MMU tests	2022-02-06 02:05:59 +00:00
Kip Macsai-Goren	52008b122a	added commenting in reference outputs that aren't simulated in spike	2022-02-06 02:05:59 +00:00
Kip Macsai-Goren	69e79ccdf3	Allowed commenting in signature files	2022-02-06 02:05:59 +00:00
David Harris	0feb624bab	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
bbracker	27dd363a85	remove sporadic tabs from tests.vh so that it is now only spaces	2022-02-05 23:07:38 +00:00
bbracker	fc2e3d1fbf	remove rv32e from regression because it is broken; goes with previous commit	2022-02-05 23:05:21 +00:00
bbracker	186267e35a	Remove rv32e tests from rv32i_m Makefrag so that make XLEN=32 works	2022-02-05 21:34:50 +00:00
David Harris	0dd8c719ad	Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit	2022-02-05 05:35:51 +00:00
David Harris	f7d6939d9b	Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts	2022-02-05 05:28:40 +00:00
David Harris	581fbb7d13	Modified wally-pipelined-batch.do to handle buildroot	2022-02-05 05:07:07 +00:00
David Harris	23868a33bc	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	16b5fee795	RV32e tests	2022-02-04 14:30:36 +00:00
James Stine	c1b3f5b655	Update synthesis script for overwrite during copy	2022-02-03 20:29:03 -06:00
David Harris	c80bbe8970	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-04 01:56:36 +00:00
David Harris	14c1d86953	rv32e	2022-02-04 01:56:30 +00:00
James Stine	dcb5005ba4	Update to 12T for synthesis	2022-02-03 19:42:03 -06:00
James Stine	b9480a4643	Added the 12T submodule to the project.	2022-02-03 19:26:41 -06:00
David Harris	f9b1b47fc9	Synth for 500 MHz	2022-02-04 01:06:13 +00:00
David Harris	dd26e9e87e	ignore .sv files in synthDC/hdl	2022-02-04 00:57:13 +00:00
David Harris	e80139cc91	Adjusted synthesis to compile rv32e on 12T library	2022-02-04 00:45:16 +00:00
David Harris	3cc20bdd0d	Added E tests to repo	2022-02-03 23:42:31 +00:00
David Harris	1c049f1f67	renamed configs	2022-02-03 23:36:41 +00:00
David Harris	e490705865	E tests	2022-02-03 22:55:55 +00:00
David Harris	c3122ce214	sram1rw cleanup	2022-02-03 18:03:22 +00:00
David Harris	0e1d784b60	sram1rw cleanup	2022-02-03 17:50:23 +00:00