Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
9,668 Commits 5 Branches 2 Tags 53 MiB
f7b93ac700
Commit Graph

62 Commits

Author SHA1 Message Date
Rose Thompson
f603d21826 Updated my name in multiple locations. 2024-08-21 10:50:39 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
David Harris
c1fd7a9589 Removed unused signals 2024-06-18 07:28:52 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
Rose Thompson
b45b7ff7d6 Signal name changes to match book. 2024-06-02 16:32:25 -05:00
Rose Thompson
84946919a4 Changed name CacheWriteData to WriteData. 2024-05-28 18:00:39 -05:00
Rose Thompson
273b41df99 Changed name of cache parameter NUMLINES to NUMSETS to better match book. 2024-05-28 17:55:43 -05:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
Rose Thompson
0d8c251fa4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-03-06 15:35:34 -06:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
Rose Thompson
4c3d927474 Renamed CacheHit to Hit. 2024-03-01 11:00:24 -06:00
Rose Thompson
85691f0e8b Simplified and clarified names in cacheLRU. 2024-02-29 17:18:01 -06:00
Rose Thompson
90ad5e7dab Updated the cache for book clarity. 2024-02-28 17:07:32 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
David Harris
3620a10c0b Improved hptw and I CacheWays coverage 2024-01-26 14:55:51 -08:00
Rose Thompson
730efefc41 Cleanup. 2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2 Restored cache store delay hazard. 2023-12-29 16:10:27 -06:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
Rose Thompson
f592baa741 Closer. 2023-12-13 18:15:32 -06:00
Rose Thompson
f3d43a7713 Progress on reducing store stall in d cache. 2023-12-13 15:34:21 -06:00
Rose Thompson
13bb5d845b On the way to solving the store delay hazard. 2023-12-13 10:39:01 -06:00
Rose Thompson
3bef2a2361 Better name for cache signals. 2023-12-03 15:49:06 -06:00
Rose Thompson
ab68a76e77 LineDirty is either the Victim Way or the Flush way dirty, but never the hitway dirty. CBO instructions require hitway dirty. However we cannot mux hitway dirty into LineDirty wihtout creating a combinational loop so we need a separate port. 2023-11-29 17:58:39 -06:00
Rose Thompson
337903d8dd More cache simplifications. 2023-11-27 14:59:42 -06:00
Rose Thompson
58d89cc347 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-21 10:48:05 -06:00
David Harris
f89fd8a7fe removed unused cache signals 2023-11-20 23:16:35 -08:00
Rose Thompson
d2a747bf3d cleanup. 2023-11-20 23:59:40 -06:00
Rose Thompson
70eb110a9c More optimizations to simplify cmo logic. 2023-11-20 22:13:31 -06:00
Rose Thompson
52ac07ce8d Removed the CMO_WRITEBACK state from the cache and unused signals. 2023-11-20 20:56:30 -06:00
Rose Thompson
23e05cb8b2 Finally have the cbo way muxing controls reduced to something sane. 2023-11-20 11:28:03 -06:00
Rose Thompson
dce3c85105 Progress. 2023-10-27 16:31:22 -05:00
Ross Thompson
914b6f9734 Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
Ross Thompson
5c408454b8 Might have working cbo clean and flush instructions. 2023-08-18 14:48:21 -05:00
Ross Thompson
f9df1fda23 CMOZ now implemented in the D cache. 2023-08-17 12:46:40 -05:00
Ross Thompson
5281077531 More progress towards cmo. 2023-08-15 18:17:15 -05:00
Ross Thompson
9f37fef145 The L1 D cache now supports cache line (block) invalidation and partial support for clean and flush. 2023-08-14 16:39:18 -05:00
Ross Thompson
0eac74ac7b Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
009d8966e9 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
19c1a0f99b Update cache.sv 
Formatting clean up
 2023-06-09 08:39:57 -07:00
Ross Thompson
052bc95966 More parameterization. Copied Lim. Still no slow down. 2023-05-24 14:49:22 -05:00
Ross Thompson
30e3d2cdce Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
Limnanthes Serafini
0b6ce1b031 Some cleanup 2023-04-13 21:01:57 -07:00
Alec Vercruysse
cc3b2bf435 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Alec Vercruysse
1cb6e1751b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
Alec Vercruysse
5b8c6f070e Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00