Katherine Parry
4ea56ac68b
some fpu lint warnings fixed - still working on it
2021-10-11 18:32:03 -07:00
Shreya Sanghai
51185478df
made redunantmul generate DW02_multp for synopsys sythnesis
2021-10-11 11:54:39 -07:00
Shreya Sanghai
295a3c7af2
actually added redundant mul
2021-10-11 11:29:13 -07:00
Shreya Sanghai
324230e2f9
added redundant multiplier
2021-10-11 11:20:12 -07:00
David Harris
fc39f77cba
Starting to optimize multiplier
2021-10-11 11:06:07 -07:00
David Harris
8a64675b02
intdiv cleanup
2021-10-11 08:14:21 -07:00
David Harris
a8ce4568aa
Divider FSM simplification
2021-10-10 22:24:14 -07:00
David Harris
a077735ecc
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
David Harris
266c706804
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:26:15 -07:00
David Harris
77f1ae54d8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:25:11 -07:00
bbracker
8eff03bf1a
simplify flopenrc's that didn't actually need to be flopenrc's
2021-10-10 12:25:05 -07:00
David Harris
93e6ec96a7
Divider cleanup
2021-10-10 12:24:44 -07:00
David Harris
6d2d93deeb
Simplifying divider FSM
2021-10-10 12:21:43 -07:00
David Harris
2d09994a91
Simplifying divider FSM
2021-10-10 12:21:36 -07:00
David Harris
644af40855
Moved & ~StallM from FSM into DivStartE
2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8
Moved divide iteration register names to M stage
2021-10-10 11:30:53 -07:00
David Harris
e8d013b106
Simplified remainder for divide by 0
2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc
divider control signal simplificaiton
2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
David Harris
99fd79c20b
Simplified divider sign handling
2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9
renamed DivStart
2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4
renamed DivSigned
2021-10-10 08:30:19 -07:00
Katherine Parry
44b023ace1
FMA matches diagram and lint warnings fixed
2021-10-09 17:38:10 -07:00
kipmacsaigoren
086e6d130a
rename adder in fpu for synthesis
2021-10-08 17:47:54 -05:00
kipmacsaigoren
8e35701103
Merging new changes into the old one's I've made in the OKstate servers
2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
3623dfa51e
removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
2021-10-08 15:33:18 -07:00
kipmacsaigoren
3103b78493
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-08 12:01:44 -05:00
bbracker
25e0745a6a
fix div restarting bug
2021-10-07 18:55:00 -04:00
kipmacsaigoren
086a0234ba
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-06 11:52:34 -05:00
James E. Stine
b90d7b8083
Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
2021-10-06 08:26:09 -05:00
kipmacsaigoren
4a9dd49785
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-04 12:28:03 -05:00
David Harris
cc41d40d61
Divider cleaup
2021-10-03 11:22:34 -04:00
David Harris
3398328bf1
Divider cleanup
2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c
Replacing XE and DE with SrcAE and SrcBE in divider
2021-10-03 11:11:53 -04:00
David Harris
bf0061be66
Reduced cycle count for DIVW/DIVUW by two
2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b
Divider comments cleanup
2021-10-03 01:12:40 -04:00
David Harris
30ec68d567
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
078ddfd341
Divider cleanup
2021-10-03 00:41:41 -04:00
David Harris
8f36297569
Added suffixes to more divider signals
2021-10-03 00:32:58 -04:00
David Harris
dcbbee6623
More divider cleanup
2021-10-03 00:20:35 -04:00
David Harris
6aa2521959
Eliminated extra inversion for subtraction in divider
2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a
Added more pipeline stage suffixes to divider
2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
3441991d93
Divider mostly cleaned up
2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7
Partial divider cleanup 3
2021-10-02 21:00:13 -04:00
David Harris
775520c05a
Partial divider cleanup 2
2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7
Partial divider cleanup
2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37
Divider code cleanup
2021-10-02 10:41:09 -04:00
David Harris
d532bde931
Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division
2021-10-02 10:36:51 -04:00
David Harris
d4437b842a
Divider code cleanup
2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d
Moved negating divider otuput to M stage
2021-10-02 10:03:02 -04:00
David Harris
735132191c
Moved muldiv result selection to M stage for performance
2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
David Harris
a39e14663d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4
Integer Divide/Rem passing all regression.
2021-09-30 20:07:22 -04:00
David Harris
953c8931ed
RV32 div/rem working signed and unsigned
2021-09-30 15:24:43 -04:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
kipmacsaigoren
afd73ddada
Merge branch 'ppa' into main
2021-09-20 01:01:47 -05:00
Ross Thompson
d09b381183
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872
Finished adding the d cache flush. Required ensuring the write data, address, and size are
...
correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
f1981a1267
more input changes on prioirty thermometer. passes lint
2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2
added new fun ways of putting inputs into the priority thermometer
2021-09-17 12:00:38 -05:00
Ross Thompson
8fa287a449
The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0
Added counters to walk through d cache flush.
2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d
Added flush controls to cachway.
2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
kipmacsaigoren
437f2d5814
changed priority circuits for synthesis and light cleanup
2021-09-15 12:24:24 -05:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
David Harris
b2fe8eddc0
Restored old integer divider
2021-09-12 22:07:52 -04:00
David Harris
1f6e4c71fc
Modified rxfull determination in UART, started division
2021-09-12 20:00:24 -04:00
Ross Thompson
225657b8f9
Fixed bug with or_rows.
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If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.
2021-09-11 15:51:11 -05:00
Ross Thompson
3b12235954
Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.
2021-09-11 15:40:27 -05:00
Ross Thompson
3ff8d0095d
Fixed dcache to prevent latches in FPGA synthesized design.
2021-09-11 12:03:48 -05:00
Ross Thompson
29efd1d222
Third attempt at fixing the write enables for the icache cacheway.
2021-09-09 15:08:10 -05:00
Ross Thompson
230c794edd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Refixed some bit width issues in the icache.
2021-09-09 12:44:02 -05:00
Ross Thompson
90f2821bea
fixed some lint bugs.
2021-09-09 12:38:57 -05:00
David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
a31828e925
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
Ross Thompson
150a73d6cf
Set associate icache working, but way 0 is never written.
2021-09-07 12:46:16 -05:00
Ross Thompson
00f50184d8
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
James E. Stine
5bc3569b0e
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
5c2deab4e4
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Katherine Parry
7607adc951
FMA cleanup
2021-08-28 10:53:35 -04:00
Ross Thompson
4b0344898b
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
2dff72d9e9
Renamed PCMux (icache) to SelAdr to match dcache.
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Removed unused cache files.
2021-08-27 11:14:10 -05:00
Ross Thompson
de9e234ffa
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
...
One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
62d91e9ea1
Renamed ICacheCntrl to icachefsm.
2021-08-26 15:57:17 -05:00
Ross Thompson
cbb47956cb
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
b230d4daec
Finished moving data path logic from the ICacheCntrl.sv to icache.sv.
2021-08-26 13:06:24 -05:00
Ross Thompson
b3849d8abb
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
c83f0a2e99
Removed unused logic in icache.
2021-08-26 10:49:54 -05:00
