Jordan Carlin
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092d10a3cd
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correct c.sext.b encoding and remove unreachable code in 01100 case
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2024-01-12 19:09:10 -08:00 |
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Rose Thompson
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a932bf6b66
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Removed unnecessary spill for compressed aligned to end of cache line or uncached access.
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2024-01-10 13:06:16 -06:00 |
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Rose Thompson
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588e1caeba
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Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries.
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2024-01-06 22:29:16 -06:00 |
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David Harris
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6181639003
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Named IFU decomp generate block
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2024-01-01 07:37:40 -08:00 |
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Rose Thompson
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6a787981c2
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Restored cache store delay hazard.
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2023-12-29 16:10:27 -06:00 |
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Rose Thompson
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f59fa5089d
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-12-29 15:13:18 -06:00 |
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Rose Thompson
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8030b7d100
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Added partial code for uncached amo operations.
Minor fix for Makefile so coverage tests build.
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2023-12-29 15:07:20 -06:00 |
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Rose Thompson
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482529394a
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Fixed some of the uncached ifu bugs.
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2023-12-29 09:53:22 -06:00 |
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David Harris
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e8df856fdb
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Renamed CMOp to CMOpM in mmu and cache
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2023-12-25 05:57:41 -08:00 |
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David Harris
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06ddccd983
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Fixed typo in IFU
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2023-12-20 20:22:17 -08:00 |
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David Harris
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8eace30f49
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Moved UnalignedPCNextF mux into IFU
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2023-12-20 16:18:31 -08:00 |
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Rose Thompson
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9f4c32d49c
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Merge branch 'main' of github.com:ross144/cvw
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2023-12-13 20:32:59 -06:00 |
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David Harris
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6c017141c5
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Renamed HADE to ADUE for Svadu
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2023-12-13 11:49:04 -08:00 |
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Rose Thompson
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3d0f9ce4f3
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Cleaned up comments about pc reset.
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2023-12-13 13:06:33 -06:00 |
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Rose Thompson
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c98c0dd3e0
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Removed unnecessary pc reset logic from ifu and btb.
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2023-12-13 13:05:10 -06:00 |
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Rose Thompson
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13bb5d845b
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On the way to solving the store delay hazard.
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2023-12-13 10:39:01 -06:00 |
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Rose Thompson
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195def5808
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Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.
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2023-11-27 21:24:30 -06:00 |
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Rose Thompson
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beb95dd592
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Modified the pmachecker to correctly check the permissions for cmo instructions.
However this isn't fully tested.
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2023-11-27 17:44:11 -06:00 |
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David Harris
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d3ce683e06
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Removed other unused signals from Verilog
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2023-11-20 23:37:56 -08:00 |
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David Harris
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f89fd8a7fe
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removed unused cache signals
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2023-11-20 23:16:35 -08:00 |
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David Harris
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8cb433cb66
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Commented IROM preloading
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2023-11-19 19:33:57 -08:00 |
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David Harris
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1f2899de14
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Modified rams to take USE_SRAM rather than P to facilitate synthesis
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2023-11-03 05:44:13 -07:00 |
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David Harris
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dd072c80f2
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Updated testbenches to capture InstrM because it may be optimized out of IFU
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2023-11-03 05:24:15 -07:00 |
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David Harris
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402538e13c
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Temporary fix of InstrM to prevent testbench hanging
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2023-11-03 04:59:44 -07:00 |
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David Harris
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09aebbf252
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Fixed regression error of watchdog timeout when PCM is optimized out of the IFU
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2023-11-03 04:38:27 -07:00 |
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David Harris
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680fb3f30b
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Conditionally instantiate hardware in ifu
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2023-10-30 20:55:00 -07:00 |
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David Harris
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afabc52b61
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Gated InstrOrigM and PCMReg when not needed
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2023-10-30 20:05:37 -07:00 |
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David Harris
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90a178e31e
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Made 2-bit AdrReg conditional on being needed
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2023-10-30 19:13:43 -07:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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David Harris
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734bf021d7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-10-26 19:02:05 -07:00 |
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David Harris
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3bb7539429
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Fixed warnings of signed conversion and for Design Compiler
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2023-10-24 14:01:43 -07:00 |
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Rose Thompson
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694ec18934
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Added support for branch counters when there is no branch predictor.
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2023-10-23 15:32:03 -05:00 |
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Rose Thompson
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1611d5ec3c
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Fixed issue 250. instruction classification was not correct for jalr ra (non zero).
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2023-10-23 15:30:43 -05:00 |
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David Harris
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28752303be
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Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
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2023-10-04 12:28:12 -07:00 |
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David Harris
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19a6bbb01b
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UpdateDA cleanup: don't assert UpdateDA when there is no SVADU
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2023-10-04 09:57:13 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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Ross Thompson
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f863cbf366
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Actually fixed non-power of 2 issue with RAS.
Added RAS swapping to branch predictor scripts and configurations.
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2023-09-27 12:25:05 -05:00 |
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Ross Thompson
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aeacb481aa
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Fixed sutble RAS bug when the stack size was not a power of 2.
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2023-09-27 12:00:47 -05:00 |
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David Harris
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8f12c6f9a1
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initial spill logic improvement
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2023-09-03 04:21:13 -07:00 |
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David Harris
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bd6eef2a51
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Initial implementation of SVNAPOT and SVPBMT does not break regression
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2023-08-25 18:33:08 -07:00 |
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Ross Thompson
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0eac74ac7b
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Initial CMO implementation. Just adds control signals into the L1 caches.
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2023-08-14 15:43:12 -05:00 |
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Ross Thompson
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7a196d3fa7
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Cache cleanup.
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2023-07-31 14:12:53 -05:00 |
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Ross Thompson
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d04d2afed2
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Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
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2023-07-21 13:06:27 -05:00 |
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Ross Thompson
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538efaf771
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Optimized critial path in ifu's spill logic.
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2023-07-19 14:13:46 -05:00 |
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Ross Thompson
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b756b248b4
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Wow. The newest version of Vivado does not like the enums as parameters.
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
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2023-07-18 15:07:10 -05:00 |
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Ross Thompson
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85567841eb
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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75b5c23edd
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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Ross Thompson
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009d8966e9
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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Ross Thompson
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b8a243827b
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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3593762cfa
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Merge branch 'main' into main
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2023-06-14 11:52:45 -07:00 |
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