David Harris
ce3edd0288
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 19:02:56 -04:00
David Harris
39fa84efdd
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 18:56:30 -04:00
David Harris
d2e3e14cbc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:55:24 -04:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
bbracker
825900565c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:17:16 -04:00
David Harris
cc04009f82
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
bbracker
11606e96f1
ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF
2021-07-04 18:17:06 -04:00
Ross Thompson
058c37b5b1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 17:07:57 -05:00
David Harris
595df47a3e
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
Ross Thompson
e198f348da
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:54:31 -05:00
Ross Thompson
2c56e30c73
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:53:16 -05:00
David Harris
71268cc0e8
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:53:08 -04:00
David Harris
6b9cfe90d8
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
Ross Thompson
f2c4df0a5b
Removed the TranslationVAdrQ as it is not necessary.
2021-07-04 16:49:34 -05:00
bbracker
a20afc6e1a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 17:20:55 -04:00
bbracker
96939328ea
for GPIO give priority to clearing interrupts
2021-07-04 17:20:16 -04:00
Ross Thompson
8e48865140
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
David Harris
d138d6545d
Restructured TLB Read as AND-OR operation with one-hot match/read line
2021-07-04 17:01:22 -04:00
David Harris
b59213c83f
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
2021-07-04 16:33:13 -04:00
David Harris
deae60eb1d
TLB cleanup
2021-07-04 14:59:04 -04:00
Ross Thompson
8ae0a5bd7d
relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
2021-07-04 13:49:38 -05:00
David Harris
243c03f870
TLB cleanup
2021-07-04 14:37:53 -04:00
David Harris
fed096407b
TLB minor organization
2021-07-04 14:30:56 -04:00
David Harris
a5c0dc8c81
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
5b891e05ac
TLB mux and swizzling cleanup
2021-07-04 12:53:52 -04:00
David Harris
622060b99f
Replaced generates with arrays in TLB
2021-07-04 12:32:27 -04:00
David Harris
b5df9b282d
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
9276446797
Switched to array notation for pmpchecker
2021-07-04 10:51:56 -04:00
David Harris
c016ab8e58
Commented out some unused modules
2021-07-04 01:40:27 -04:00
David Harris
1bd353c1d7
Merge conflict on linux-waves.do
2021-07-04 01:22:10 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
bbracker
17ef10568f
optionally output GDB-formatted instruction list to main buildroot folder
2021-07-03 17:25:19 -04:00
Ross Thompson
9b959715a0
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
Ross Thompson
fd088f8ecd
Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.
2021-07-03 15:51:25 -05:00
Ben Bracker
66692af57c
src/cache/ICacheCntrl.sv
2021-07-03 11:24:41 -05:00
Ben Bracker
d6c7dc02ed
fix ICache indenting
2021-07-03 11:11:07 -05:00
David Harris
ee605d7550
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
David Harris
d3dedc1637
Cleaned up PMA/PMP checker unused code
2021-07-03 02:25:31 -04:00
Ben Bracker
9709bd78e1
stop busybear from hanging
2021-07-02 17:22:09 -05:00
David Harris
4ec570d2d7
Fixed PMPCFG read faults
2021-07-02 17:08:13 -04:00
Ross Thompson
16e672ada0
Fixed up the physical address generation for 64 bit page table walker.
2021-07-02 15:49:32 -05:00
Ross Thompson
a8fbbb0631
Fixed up the bit widths on the page table walker for rv32.
2021-07-02 15:45:05 -05:00
Ross Thompson
46831035fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
Katherine Parry
4a6abe0f50
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-02 12:56:53 -04:00
Katherine Parry
72406b8a88
FPU update - missing files
2021-07-02 12:53:05 -04:00
Ross Thompson
549b7b2a62
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
David Harris
1ce98cc100
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-02 12:52:20 -04:00
Katherine Parry
3f61e313d2
FPU update
2021-07-02 12:40:58 -04:00
David Harris
cd6cabac2f
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:05:25 -04:00
David Harris
648c09e5ef
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
2616f41f91
reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first.
2021-07-01 18:04:43 -05:00
Ross Thompson
386193de00
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
3dae02818c
OMG. It's working!
2021-07-01 17:37:53 -05:00
Ross Thompson
9139cd2954
Fixed tab space issue.
2021-07-01 17:17:53 -05:00
Ross Thompson
c3eaa3169e
Fixed the wrong virtual address write into the dtlb.
2021-07-01 16:55:16 -05:00
Teo Ene
1d5d7a7840
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
Ross Thompson
9d9415ea67
Got some stores working in virtual memory.
2021-07-01 12:49:09 -05:00
Ross Thompson
be6468c6d9
Icache ITLB interlock fix.
2021-06-30 19:24:59 -05:00
Ross Thompson
4530e43df6
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
6216bd7172
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
ae6140bd94
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
bbracker
a7f810e2c4
trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug
2021-06-26 08:30:58 -04:00
bbracker
aa8da43743
temporarily disable PMP checking for EBU accesses.
2021-06-26 07:19:51 -04:00
bbracker
59b2a49854
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
Ross Thompson
8dfbf60b67
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Ross Thompson
a4266c0136
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
9fd1761fd6
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
9927f771cc
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
4e09793a9a
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
aac9b46a1f
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
1485d29dde
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
389b9a510e
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
bc8d660bc5
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
ced5039776
Revert "fixed forwarding"
...
This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
732551d6be
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
3ae4cd951a
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
3d6b422e34
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
409a73604c
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
55cf205222
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
b84419ff4e
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
44af47608c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
5de7a46237
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
718630c378
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
4189b2d4a7
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
1972d83002
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
