Ross Thompson
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dc48d84dd6
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Modified clint to support all byte write sizes.
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2022-03-31 11:31:52 -05:00 |
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bbracker
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54b9745a75
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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b2a77da96b
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Changed sram1p1rw to have the same type of bytewrite enables as bram.
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2022-03-30 11:38:25 -05:00 |
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Ross Thompson
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3ac736e2d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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370a075fa1
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Partial cleanup of memories.
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2022-03-30 11:09:21 -05:00 |
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Ross Thompson
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1993069986
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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fc2b4453ec
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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de2672231d
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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David Harris
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049c55769a
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fpu compare simplification, minor cleanup
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2022-03-29 17:11:28 +00:00 |
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Kip Macsai-Goren
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ad106e7130
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made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes
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2022-03-29 02:26:42 +00:00 |
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bbracker
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46ffa4b079
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fix typo that Madeleine found
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2022-03-28 15:39:29 -07:00 |
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Kip Macsai-Goren
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dc9635b757
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fixed double multiplication on vectored interrupts
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2022-03-28 19:12:31 +00:00 |
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Ross Thompson
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7099259ff7
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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
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2022-03-25 13:10:31 -05:00 |
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Ross Thompson
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7a824eaae1
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Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
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2022-03-24 23:47:28 -05:00 |
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bbracker
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150a7b234b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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9f60256f22
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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58668812c1
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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07b7dbc922
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-23 14:10:38 -05:00 |
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Katherine Parry
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abdbc31d14
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fixed typo in unpack.sv
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2022-03-23 18:26:59 +00:00 |
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Katherine Parry
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ead88fba55
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fixed lint error in fpudivsqrtrecur.sv
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2022-03-23 03:24:41 +00:00 |
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Ross Thompson
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6ab14d7302
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Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
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2022-03-22 22:04:06 -05:00 |
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Ross Thompson
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c5be2cb1d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-22 21:28:50 -05:00 |
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Katherine Parry
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c3c764a171
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unpack.sv cleanup
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2022-03-23 01:53:37 +00:00 |
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Ross Thompson
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cec7625d91
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Added comment about needed fix to misaligned fault.
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2022-03-22 16:52:07 -05:00 |
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Katherine Parry
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2042374102
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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d347de8c49
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dtim writes are supressed on non cacheable operation.
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2022-03-12 00:46:11 -06:00 |
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Ross Thompson
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d8947fa616
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cleanup of ram.sv
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2022-03-11 18:09:22 -06:00 |
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Ross Thompson
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e802deb4d6
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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Ross Thompson
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3dbf6790e1
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Towards allowing dtim + bus.
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2022-03-11 14:58:21 -06:00 |
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Ross Thompson
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81a2fbb6d2
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mild cleanup.
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2022-03-11 13:05:47 -06:00 |
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Ross Thompson
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11e5aad38a
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Moved subcachelineread inside the cache. There is some ugliness to still resolve.
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2022-03-11 12:44:04 -06:00 |
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Ross Thompson
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a12016e69b
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Moved subcacheline read inside the cache.
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2022-03-11 11:03:36 -06:00 |
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Ross Thompson
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326ecda060
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removed unused parameter.
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2022-03-11 10:43:54 -06:00 |
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Ross Thompson
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04dd2f0eb5
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atomic cleanup.
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2022-03-10 18:56:37 -06:00 |
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Ross Thompson
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a598760445
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Name changes.
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2022-03-10 18:50:03 -06:00 |
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Ross Thompson
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bdfca503fa
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Name cleanup.
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2022-03-10 18:44:50 -06:00 |
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Ross Thompson
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d77adbd673
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Signal name cleanup.
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2022-03-10 18:26:58 -06:00 |
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Ross Thompson
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5c16b65a16
|
simplified uncore's name for HWDATA.
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2022-03-10 18:17:44 -06:00 |
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Ross Thompson
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543e10ab32
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Moved subwordwrite to lsu directory.
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2022-03-10 18:15:25 -06:00 |
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Ross Thompson
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54abd944e2
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Simplified byte write enable logic.
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2022-03-10 18:13:35 -06:00 |
|
Ross Thompson
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50789f9ddd
|
Byte write enables are passing all configs now.
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2022-03-10 17:26:32 -06:00 |
|
Ross Thompson
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f7df3a0666
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Progress on the path to getting all configs working with byte write enables.
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2022-03-10 17:02:52 -06:00 |
|
Ross Thompson
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83133f8c47
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Partially working byte write enables. Works for cache, but not dtim or bus only.
|
2022-03-10 16:11:39 -06:00 |
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Ross Thompson
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d5f524a15e
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Added byte write enables to cache SRAMs.
|
2022-03-10 15:48:31 -06:00 |
|
David Harris
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b1340653cf
|
bit write update
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2022-03-09 19:09:20 +00:00 |
|
David Harris
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004853c312
|
Refactored SRAM bit write enable
|
2022-03-09 17:49:28 +00:00 |
|
David Harris
|
ba9320d822
|
Updated testbench to read expected flags
|
2022-03-09 13:58:17 +00:00 |
|
Ross Thompson
|
2a8a1cd191
|
Minor cleanup to interlockfsm.
|
2022-03-08 23:38:58 -06:00 |
|
Ross Thompson
|
ac9528b450
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-08 18:05:35 -06:00 |
|
Ross Thompson
|
ed32801cc1
|
Comments.
|
2022-03-08 18:05:25 -06:00 |
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