Teo Ene
af3a888cde
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
6c3c319d70
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
84d856d1e5
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
4bfed99da3
add reference output for some tests
2021-02-12 18:33:24 +00:00
Noah Boorstin
dd3a5b74a1
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
79fb83409f
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Noah Boorstin
f08e549118
gdb output combine script updates
...
check that everything is actually the same instruction
update to new 4-file output
this file should be finished for now
2021-02-11 14:59:15 -05:00
Tejus Rao
fb6a4bbbf0
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
3e29e28132
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-02-10 20:49:12 -06:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
Teodor-Dumitru Ene
cdc96d306a
Added hex code for the pre-compiled, provided, CoreMark binary
2021-02-10 21:22:38 -05:00
Teo Ene
50d00acb31
Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions:
...
- RV64I
2021-02-10 20:12:07 -06:00
ethan-falicov
7925fe3131
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
David Harris
b121b90b28
Debugging bus interface.
2021-02-10 01:43:54 -05:00
James E. Stine
475da788e2
Add ppt and mp4 of wavedrom usage
2021-02-09 13:15:29 -06:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
74bc4c0444
Fixed lw by delaying read value by one cycle
2021-02-07 23:28:21 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
Jarred Allen
e334475ab5
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4
merge conflict?
2021-02-07 02:34:49 -05:00
Noah Boorstin
01b1b1705d
Busybear: next week of updates
...
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
Jarred Allen
29b7a0cd25
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
a3f2f4c7bc
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
Noah Boorstin
52ffb617d9
Update parsing thingy to use split GDB runs
...
huge thanks to kaveh for all his work on this yesterday
2021-02-05 16:46:57 -05:00
James E. Stine
493bab529e
Updates to wavedrom
2021-02-05 10:56:29 -06:00
bbracker
15c0b4af22
JAL testing
2021-02-05 08:08:42 -05:00
Noah Boorstin
c03f69fb80
Change CSR reset and available bits to conform to OVPsim
...
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
2021-02-04 22:03:45 +00:00
James E. Stine
a886e222c1
sorry ; last update
2021-02-04 15:20:15 -06:00
James E. Stine
44f0ac98b0
Update as overwrite a file :(
2021-02-04 15:11:06 -06:00
James E. Stine
f55dffadee
Updates to wavedrom for typos
2021-02-04 14:49:17 -06:00
James E. Stine
752552970c
Add some example wavedrom files - more on the way including ppt
2021-02-04 14:41:42 -06:00
Thomas Fleming
8d7a515ae7
Complete STORE tests
2021-02-04 15:38:22 -05:00
Noah Boorstin
fc734eb14e
busybear: add more CSRs
2021-02-04 20:13:36 +00:00
Noah Boorstin
77a88d8019
busybear: check initial values also
2021-02-04 19:22:09 +00:00
Brett Mathis
11e2666bb2
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Jarred Allen
088fbbcbf0
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
f700efc2b3
Start on a test set for loads
2021-02-03 00:37:43 -05:00
David Harris
2a80bcf543
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
756352f129
Minor tweaks
2021-02-02 19:44:37 -05:00
Jarred Allen
e5bd749e2a
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9
Add busybear testbench to nightly regression checking
...
If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Noah Boorstin
b5f474d9f5
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55
change undefined syntax in extend.sv
...
don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
