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Configurable RISC-V Processor
123 Commits 4 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
c03f69fb80
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Noah Boorstin c03f69fb80 Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
2021-02-04 22:03:45 +00:00
riscv-o3@afb27bd558 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Change CSR reset and available bits to conform to OVPsim 2021-02-04 22:03:45 +00:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor