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Configurable RISC-V Processor
114 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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David Harris 429f48e766 Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
riscv-o3@afb27bd558 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor