Thomas Fleming
d53afc8510
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
81ed9b5d06
coremark directory changes
2021-05-03 19:35:06 -04:00
Ross Thompson
21c0ee0cf2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
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I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Thomas Fleming
3f7061d557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Jarred Allen
a21b84e2ad
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
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Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
1db608fbc6
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
fdf4954a20
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Noah Boorstin
c9fcd3405d
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Thomas Fleming
10c7260980
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-29 16:30:00 -04:00
Domenico Ottolia
99a927be47
Add medeleg tests
2021-04-29 15:02:36 -04:00
Jarred Allen
c6996ce39d
Remove signal which no longer exists from default waves, so sim-wally works
2021-04-29 14:41:10 -04:00
Thomas Fleming
d29ddddc3f
Remove unused waves from .do files
2021-04-29 02:19:46 -04:00
Thomas Fleming
6515c0b9ed
Add mmu waves (commented) to busybear
2021-04-28 20:01:05 -04:00
Ross Thompson
d191bc6cc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
24bbb674d3
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Noah Boorstin
9cbc769083
minor busybear fixes
2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
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Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
46a1616079
thomas fixed it before I did
2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
Ross Thompson
d7fea1ba3c
almost working icache.
2021-04-23 16:47:23 -05:00
Jarred Allen
9a88d83851
Remind people to run make allclean when a regression fails
2021-04-22 19:21:00 -04:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Jarred Allen
8baa2a350d
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Ross Thompson
7c8d2e9b78
Partially working icache.
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The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Ross Thompson
50e893eec9
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Ross Thompson
269ea7997c
major progress.
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It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Ross Thompson
a861a37b72
Why was the linter messed up?
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There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
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yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
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This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Jarred Allen
6ce4d44ae1
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Ross Thompson
75b97f1422
Created special test for driving the instruction spill error.
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The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.
0000000000000080 <test_spill>:
80: 42a9 li t0,10
82: 0001 nop
84: 0001 nop
86: 0001 nop
88: 02bd addi t0,t0,15
8a: 00628e33 add t3,t0,t1
8e: 01ce8963 beq t4,t3,a0 <match>
0000000000000092 <failure>:
92: 557d li a0,-1
94: 8082 ret
96: 00000013 nop
9a: 00000013 nop
9e: 0001 nop
00000000000000a0 <match>:
a0: 1ffd addi t6,t6,-1
a2: fc0f9fe3 bnez t6,80 <test_spill>
a6: 4501 li a0,0
a8: 8082 ret
Instructions 0x88, 0x8a and 0x8e are read incorrectly. However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92. This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.
The button of wavefile wave.do shows the exact problem in the 'icache'.
2021-04-08 15:05:08 -05:00
bbracker
37bca569ff
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 14:28:25 -04:00
bbracker
c8c87bd0d8
merge testbench
2021-04-08 14:28:01 -04:00
David Harris
2203e64b65
merge conflict resolution
2021-04-08 13:53:56 -04:00
David Harris
aabebdb59f
fixed sim-wally-32ic
2021-04-08 13:40:16 -04:00
