David Harris
5d4014d351
Refactoring ALU and datapath muxes
2021-12-08 12:33:53 -08:00
Ross Thompson
8e4eacc18e
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Noah Limpert
cb77c1db3a
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
slmnemo
870549c01a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
Noah Limpert
0ccc7d5fe8
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
Noah Limpert
832b23b8a4
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
3f76549a7d
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
b8572d6a2a
Changed several things.
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Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Noah Limpert
21ea270fe2
Have replaced .* with signal names in ifu
2021-10-27 13:45:37 -07:00
Ross Thompson
2f4ee26b60
Fixed issue with dtim (fpga) external abhlite select not triggering.
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Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
Ross Thompson
f7583d0e0d
Updated uncore to use sdc.
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Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
David Harris
47124f36c8
Added synchronizer to reset
2021-10-25 10:05:41 -07:00
David Harris
8b1dc81d34
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
b6bb33ecef
lint cleanup
2021-10-23 11:03:28 -07:00
David Harris
5e961973cb
IEU lint cleanup
2021-10-23 10:51:53 -07:00
David Harris
708b914a65
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
817795f619
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
687703f0d8
removed .* from wallypipeliendsoc
2021-10-20 13:49:18 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
David Harris
24bb3f4baf
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
Ross Thompson
db18aac9af
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
Ross Thompson
99070127d8
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
Ross Thompson
f2c1ca4bd5
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
6dc25e07c2
Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
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the flash card to dram.
Fixed latch issue in the sd card reader.
2021-09-26 13:22:23 -05:00
Ross Thompson
55f3c15302
Merge branch 'sdc' into fpga
2021-09-25 19:33:07 -05:00
Ross Thompson
4256ef82b1
SDC to ABHLite interface partially done.
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Added SDC to adrdec and uncore.
2021-09-24 10:45:09 -05:00
Ross Thompson
d4f514010d
Changes to make fpga synthesizable.
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Added preload to test simple program on wally in fpga.
2021-09-22 10:54:13 -05:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
6f9983628e
Removed one more genout bit.
2021-09-11 18:42:47 -05:00
Ross Thompson
759b45ca36
Added calibration input.
...
fixed HRESP duplication.
2021-09-11 15:59:27 -05:00
Ross Thompson
b04e00d196
Third attempt at fixing the write enables for the icache cacheway.
2021-09-09 15:49:27 -05:00
Ross Thompson
bf312bb37c
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
bb3e94d68a
Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
2021-08-23 15:46:17 -05:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
David Harris
49ec45d04d
hptw: Removed NonBusTrapM from LSU
2021-07-17 15:22:24 -04:00
David Harris
e55546da34
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
bf56000f4e
hptw: Propagating PageTableEntryF removal through LSU
2021-07-17 15:01:01 -04:00
David Harris
fe8910437a
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
David Harris
52fcc47cdf
Removed rest of HRDATAW from ahblite
2021-07-17 02:15:24 -04:00
Ross Thompson
4549a9f1c9
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
c954fb510b
Renamed DCacheStall to LSUStall in hart and hazard.
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Added missing logic in lsu.
2021-07-15 10:16:16 -05:00
Katherine Parry
f8b76082e4
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
