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Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Ross Thompson
2752e5de4c Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
c0966c32e5 Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
538efaf771 Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
97a16f75dc Fixed typo in fpga top for arty a7. 2023-07-19 11:37:29 -05:00
Ross Thompson
e4d6a9f8c6 Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
af0e33209f Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
Ross Thompson
6572b34751 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-18 17:16:33 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
026570d3da Added new submodule for digilent fpga boards. 2023-07-17 16:25:37 -05:00
Ross Thompson
5bc7e251fa Merge branch 'main' of github.com:ross144/cvw 2023-07-17 16:01:05 -05:00
Ross Thompson
d1ea52f6ea Added artya7 device tree. 2023-07-17 16:01:02 -05:00
Ross Thompson
6a2b752fc0 Updated arty a7 fpga top. 2023-07-17 15:55:57 -05:00
Ross Thompson
42e6364b3d Merge branch 'main' of github.com:ross144/cvw 2023-07-17 15:52:27 -05:00
Ross Thompson
c82638774f Updated the FPGA zero stage bootloader. 2023-07-17 15:52:13 -05:00
David Harris
3dde7c59a8 Merge pull request #363 from ross144/main 
Fixed over logging issue with icache and dcache loggers.
 2023-07-15 06:19:11 -07:00
Ross Thompson
50bc679fef Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations. 2023-07-14 16:31:44 -05:00
Ross Thompson
59022099c7 Fixed the icache and dcache overlogging issue. 2023-07-14 15:47:05 -05:00
Ross Thompson
141c1b9dfb Somehow the Arty A7 device tree was missing. 2023-07-13 14:10:45 -05:00
Ross Thompson
da7c6d33cd Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-13 11:26:49 -05:00
Ross Thompson
f851245a95 Merge pull request #361 from davidharrishmc/dev 
Clean up privilege rs1 decoding and implement svinval as sfence.vma
 2023-07-13 12:26:30 -04:00
David Harris
644afa16cd Clean up privilege rs1 decoding and implement svinval as sfence.vma 2023-07-13 02:41:17 -07:00
David Harris
b65d43f59b Merge pull request #360 from ross144/main 
Fixed the privilege decoder bug which prevented the fpga linux boot.
 2023-07-13 01:40:28 -07:00
Ross Thompson
9533dee300 Got xcelium running wally, but it fails to actually preload the memories. 2023-07-12 13:56:57 -05:00
Ross Thompson
33d8e5687e Merge branch 'main' of github.com:ross144/cvw 2023-07-11 15:09:07 -05:00
Ross Thompson
99073a70c0 Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
38f32805ae Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
4653f8e704 Simplificaiton of function tracker. 2023-07-11 10:51:17 -05:00
Ross Thompson
4c4eb080ee RTL changes for Xcelium. 2023-07-11 10:51:02 -05:00
Ross Thompson
12beada55b Fixed the privilege decoder bug which prevented the fpga linux boot. 2023-07-10 17:00:06 -05:00
Ross Thompson
beaec570c7 Merge pull request #359 from davidharrishmc/dev 
CSR updates
 2023-07-10 13:16:57 -04:00
David Harris
e713ba8d3e MENVCFG only exists if U_SUPPORTED 2023-07-09 18:25:07 -07:00
David Harris
4faf7c2ac6 Merge pull request #358 from ross144/main 
Fixes the FPGA linux boot after parameterization.  Note commit 15314a9c breaks the FPGA again
 2023-07-07 17:09:57 -07:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
9a49ec0b98 Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
cb22463763 Fixed slight bug in config from parameterization. 2023-07-07 16:33:34 -05:00
Ross Thompson
235546fa06 Merge branch 'main' of github.com:ross144/cvw 2023-07-07 13:25:00 -05:00
Ross Thompson
cdf73d3b51 Updated comments. 2023-07-06 15:24:26 -05:00
Ross Thompson
e4555dc4af Removed unused parameter. 2023-07-06 14:57:07 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
369e8fb5ec Removed outdated commment about endianness 2023-07-06 12:41:46 -07:00
David Harris
869a7cb827 Removed MTINST, which is not used in a system without a hypervisor 2023-07-06 12:40:53 -07:00
Ross Thompson
a963e50e88 It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. 2023-07-06 14:07:37 -05:00
Ross Thompson
df56ff73c0 This is at least functionally correct, but has verilator lint issues. 2023-07-06 11:53:34 -05:00
Ross Thompson
c000366d3e closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
98147e116a Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
Ross Thompson
6a2eca5657 Merge pull request #355 from davidharrishmc/dev 
Decoder improvements
 2023-07-05 00:08:49 -04:00
David Harris
269bb688ea Fixed comment typo 2023-07-04 11:34:58 -07:00
David Harris
b04763bcf2 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00