mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:ross144/cvw
This commit is contained in:
Ross Thompson
commit
5bc7e251fa
58
.gitignore
vendored
58
.gitignore
vendored
@ -59,6 +59,9 @@ examples/C/sum/sum
|
||||
examples/C/fir/fir
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/fpcalc/fpcalc
|
||||
examples/C/inline/inline
|
||||
examples/C/sum_mixed/sum_mixed
|
||||
examples/asm/trap/trap
|
||||
src/fma/fma16_testgen
|
||||
linux/devicetree/debug/*
|
||||
!linux/devicetree/debug/dump-dts.sh
|
||||
@ -114,4 +117,57 @@ sim/vsim.log
|
||||
tests/coverage/*.elf
|
||||
*.elf.memfile
|
||||
sim/*Cache.log
|
||||
sim/branch
|
||||
sim/branch
|
||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
/sim/branch-march14.tar.gz
|
||||
/sim/gshareforward-no-class
|
||||
/sim/lint-wally_32
|
||||
/sim/lint-wally_32e
|
||||
/sim/local16.txt
|
||||
/sim/localhistory_m6k10_results_april24.txt
|
||||
/sim/log.log
|
||||
/sim/obj_dir/Vtestbench.cpp
|
||||
/sim/obj_dir/Vtestbench.h
|
||||
/sim/obj_dir/Vtestbench.mk
|
||||
/sim/obj_dir/Vtestbench__ConstPool_0.cpp
|
||||
/sim/obj_dir/Vtestbench__Syms.cpp
|
||||
/sim/obj_dir/Vtestbench__Syms.h
|
||||
/sim/obj_dir/Vtestbench___024root.h
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024root__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024unit.h
|
||||
/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench___024unit__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench__verFiles.dat
|
||||
/sim/obj_dir/Vtestbench_classes.mk
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
|
||||
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
|
||||
|
||||
3
.gitmodules
vendored
3
.gitmodules
vendored
@ -24,3 +24,6 @@
|
||||
[submodule "addins/branch-predictor-simulator"]
|
||||
path = addins/branch-predictor-simulator
|
||||
url = https://github.com/synxlin/branch-predictor-simulator.git
|
||||
[submodule "addins/FreeRTOS-Kernel"]
|
||||
path = addins/FreeRTOS-Kernel
|
||||
url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
|
||||
|
||||
36
Makefile
36
Makefile
@ -4,7 +4,11 @@
|
||||
|
||||
all:
|
||||
make install
|
||||
make regression
|
||||
make testfloat
|
||||
make riscof
|
||||
make verify
|
||||
make coverage
|
||||
make benchmarks
|
||||
|
||||
# install copies over the Makefile.include from riscv-isa-sim
|
||||
# And corrects the TARGETDIR path and the RISCV_PREFIX
|
||||
@ -18,9 +22,37 @@ install:
|
||||
##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
|
||||
##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
|
||||
|
||||
regression:
|
||||
riscof:
|
||||
make -C sim
|
||||
|
||||
testfloat:
|
||||
cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
|
||||
cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
|
||||
cd ${WALLY}/tests/fp; ./create_all_vectors.sh
|
||||
|
||||
verify:
|
||||
cd ${WALLY}/sim; ./regression-wally
|
||||
cd ${WALLY}/sim; ./sim-testfloat-batch all
|
||||
make imperasdv
|
||||
|
||||
imperasdv:
|
||||
iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
|
||||
iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
|
||||
|
||||
coverage:
|
||||
cd ${WALLY}/sim; ./regresssion-wally -coverage -fp
|
||||
|
||||
benchmarks:
|
||||
make coremark
|
||||
make embench
|
||||
|
||||
coremark:
|
||||
cd ${WALLY}/benchmarks/coremark; make; make run
|
||||
|
||||
embench:
|
||||
cd ${WALLY}/benchmarks/embench; make; make run
|
||||
|
||||
|
||||
clean:
|
||||
make clean -C sim
|
||||
|
||||
|
||||
@ -33,7 +33,7 @@ Then clone the repo, source setup, make the tests and run regression
|
||||
|
||||
On the Linux computer where you will be working, log in
|
||||
|
||||
Clone your fork of the repo and run the setup script.
|
||||
Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id.
|
||||
|
||||
$ cd
|
||||
$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
|
||||
|
||||
1
addins/FreeRTOS-Kernel
Submodule
1
addins/FreeRTOS-Kernel
Submodule
@ -0,0 +1 @@
|
||||
Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31
|
||||
@ -1 +1 @@
|
||||
Subproject commit a3b7f0c2cf89652b8a0cba3146890c512ff8ba44
|
||||
Subproject commit 873d16e748ad60023dcdda3926144957c096e31d
|
||||
@ -3,15 +3,19 @@
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
PORT_DIR = $(CURDIR)/riscv64-baremetal
|
||||
cmbase=../../addins/coremark
|
||||
work_dir= ../../benchmarks/coremark/work
|
||||
cmbase= $(WALLY)/addins/coremark
|
||||
work_dir= $(WALLY)/benchmarks/coremark/work
|
||||
XLEN ?=64
|
||||
sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
|
||||
$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
|
||||
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
|
||||
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
|
||||
ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
|
||||
ARCH := rv$(XLEN)im
|
||||
#ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs
|
||||
#ARCH := rv$(XLEN)gc
|
||||
ARCH := rv$(XLEN)imc_zicsr
|
||||
#ARCH := rv$(XLEN)im_zicsr
|
||||
#ARCH := rv$(XLEN)i_zicsr
|
||||
PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
|
||||
-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
|
||||
-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
|
||||
@ -23,9 +27,6 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile
|
||||
|
||||
run:
|
||||
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
||||
cd ../benchmarks/coremark/
|
||||
# KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
|
||||
python3 coremark-postprocess.py
|
||||
|
||||
$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
|
||||
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
|
||||
@ -33,13 +34,14 @@ $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
|
||||
extractFunctionRadix.sh $<.elf.objdump
|
||||
|
||||
$(work_dir)/coremark.bare.riscv: $(sources) Makefile
|
||||
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)"
|
||||
make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV) XCFLAGS="$(PORT_CFLAGS)"
|
||||
mkdir -p $(work_dir)
|
||||
mv $(cmbase)/coremark.bare.riscv $(work_dir)
|
||||
|
||||
.PHONY: clean
|
||||
|
||||
clean:
|
||||
make -C $(cmbase) clean
|
||||
rm -f $(work_dir)/*
|
||||
|
||||
|
||||
|
||||
@ -1,58 +0,0 @@
|
||||
#!/usr/bin/env python
|
||||
#########################################################
|
||||
#
|
||||
# coremark postprocessing script
|
||||
#
|
||||
# Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
#
|
||||
# Created 2022-09-25
|
||||
#
|
||||
# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##################################################
|
||||
|
||||
logFile = "../../benchmarks/coremark/work/coremark.sim.log"
|
||||
|
||||
with open(logFile, "r") as logRead:
|
||||
logLines = logRead.readlines()
|
||||
|
||||
for lineNum in range(len(logLines)):
|
||||
contents = logLines[lineNum].lower().split()
|
||||
if "branches" in contents and "miss" in contents:
|
||||
branchMisses = int(contents[-1])
|
||||
elif "branches" in contents:
|
||||
branchesTot = int(contents[-1])
|
||||
branchLineNum = lineNum + 2
|
||||
|
||||
if "d-cache" in contents and "misses" in contents:
|
||||
dCacheMisses = int(contents[-1])
|
||||
elif "d-cache" in contents:
|
||||
dCacheAccess = int(contents[-1])
|
||||
dCacheLineNum = lineNum + 2
|
||||
|
||||
if "i-cache" in contents and "misses" in contents:
|
||||
ICacheMisses = int(contents[-1])
|
||||
elif "i-cache" in contents:
|
||||
ICacheAccess = int(contents[-1])
|
||||
ICacheLineNum = lineNum + 2
|
||||
|
||||
# need to add the number of previously added lines to the line number so that they stay in the intedned order.
|
||||
logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n")
|
||||
logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")
|
||||
logLines.insert(dCacheLineNum+2, "# D-cache Hit Rate " + str((dCacheAccess - dCacheMisses) / dCacheAccess) + "\n")
|
||||
|
||||
logLines.insert(ICacheLineNum+3, "# I-cache Hits " + str(ICacheAccess - ICacheMisses) + "\n")
|
||||
logLines.insert(ICacheLineNum+4, "# I-cache Miss Rate " + str(ICacheMisses / ICacheAccess) + "\n")
|
||||
logLines.insert(ICacheLineNum+5, "# I-cache Hit Rate " + str((ICacheAccess - ICacheMisses) / ICacheAccess) + "\n")
|
||||
|
||||
logLines.insert(branchLineNum+6, "# Branches Miss/Total ratio " + str(branchMisses / branchesTot) + "\n")
|
||||
|
||||
|
||||
with open(logFile, "w") as logWrite:
|
||||
logWrite.writelines(logLines)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -84,6 +84,11 @@ void setStats(int enable)
|
||||
READ_CTR(mhpmcounter10);
|
||||
READ_CTR(mhpmcounter11);
|
||||
READ_CTR(mhpmcounter12);
|
||||
READ_CTR(mhpmcounter13);
|
||||
READ_CTR(mhpmcounter14);
|
||||
READ_CTR(mhpmcounter15);
|
||||
READ_CTR(mhpmcounter16);
|
||||
READ_CTR(mhpmcounter17);
|
||||
|
||||
#undef READ_CTR
|
||||
}
|
||||
@ -167,18 +172,21 @@ void _init(int cid, int nc)
|
||||
counters[12] = read_csr(mhpmcounter12) - counters[12];
|
||||
counters[13] = read_csr(mhpmcounter13) - counters[13];
|
||||
counters[14] = read_csr(mhpmcounter14) - counters[14];
|
||||
counters[15] = read_csr(mhpmcounter15) - counters[15];
|
||||
counters[16] = read_csr(mhpmcounter16) - counters[16];
|
||||
counters[17] = read_csr(mhpmcounter17) - counters[17];
|
||||
|
||||
ee_printf("Load Stalls %d\n", counters[3]);
|
||||
ee_printf("D-Cache Accesses %d\n", counters[11]);
|
||||
ee_printf("D-Cache Misses %d\n", counters[12]);
|
||||
ee_printf("I-Cache Accesses %d\n", counters[13]);
|
||||
ee_printf("I-Cache Misses %d\n", counters[14]);
|
||||
ee_printf("Branches %d\n", counters[5]);
|
||||
ee_printf("Branches Miss Predictions %d\n", counters[4]);
|
||||
ee_printf("BTB Misses %d\n", counters[6]);
|
||||
ee_printf("Jump, JAL, JALR %d\n", counters[7]);
|
||||
ee_printf("RAS Wrong %d\n", counters[8]);
|
||||
ee_printf("Returns %d\n", counters[9]);
|
||||
ee_printf("Load Stalls %d\n", counters[11]);
|
||||
ee_printf("D-Cache Accesses %d\n", counters[13]);
|
||||
ee_printf("D-Cache Misses %d\n", counters[14]);
|
||||
ee_printf("I-Cache Accesses %d\n", counters[16]);
|
||||
ee_printf("I-Cache Misses %d\n", counters[17]);
|
||||
ee_printf("Branches %d\n", counters[3]);
|
||||
ee_printf("Branches Miss Predictions %d\n", counters[7]);
|
||||
ee_printf("BTB Misses %d\n", counters[8]);
|
||||
ee_printf("Jump and JR %d\n", counters[4]);
|
||||
ee_printf("RAS Wrong %d\n", counters[9]);
|
||||
ee_printf("Returns %d\n", counters[5]);
|
||||
ee_printf("BP Class Wrong %d\n", counters[10]);
|
||||
ee_printf("Done printing performance counters\n");
|
||||
|
||||
|
||||
@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size
|
||||
# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
|
||||
build_speedopt_speed:
|
||||
$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles"
|
||||
# remove files not used in embench1.0 When changing to 2.0, restore these files
|
||||
#rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum
|
||||
#rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind
|
||||
#rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount
|
||||
find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
|
||||
|
||||
build_sizeopt_speed:
|
||||
$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles"
|
||||
# remove files not used in embench1.0 When changing to 2.0, restore these files
|
||||
#rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum
|
||||
#rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind
|
||||
#rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount
|
||||
find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
|
||||
|
||||
# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
|
||||
|
||||
@ -279,12 +279,13 @@ if(sys.argv[1] == '-b'):
|
||||
dct[PredType] = (currSize, currPercent)
|
||||
print(dct)
|
||||
fig, axes = plt.subplots()
|
||||
marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*'}
|
||||
colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue'}
|
||||
marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
|
||||
colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
|
||||
for cat in dct:
|
||||
(x, y) = dct[cat]
|
||||
x=[int(2**int(v)) for v in x]
|
||||
print(x, y)
|
||||
#print(x, y)
|
||||
print(cat)
|
||||
axes.plot(x,y, color=colors[cat])
|
||||
axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
|
||||
#plt.scatter(x, y, label=cat)
|
||||
|
||||
@ -29,7 +29,7 @@
|
||||
|
||||
# Use /opt/riscv for installation - may require running script with sudo
|
||||
export RISCV="${1:-/opt/riscv}"
|
||||
export PATH=$PATH:$RISCV/bin
|
||||
export PATH=$PATH:$RISCV/bin:/usr/bin
|
||||
|
||||
set -e # break on error
|
||||
|
||||
@ -40,25 +40,25 @@ NUM_THREADS=8 # for >= 32GiB
|
||||
#NUM_THREADS=16 # for >= 64GiB
|
||||
|
||||
sudo mkdir -p $RISCV
|
||||
# *** need to update permissions to local user
|
||||
|
||||
# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
|
||||
apt update -y
|
||||
apt upgrade -y
|
||||
apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator
|
||||
|
||||
sudo apt update -y
|
||||
sudo apt upgrade -y
|
||||
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
|
||||
# Other python libraries used through the book.
|
||||
pip3 install matplotlib scipy scikit-learn adjustText lief
|
||||
sudo pip3 install matplotlib scipy scikit-learn adjustText lief
|
||||
|
||||
# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
|
||||
if ! command -v python &> /dev/null
|
||||
then
|
||||
echo "WARNING: python3 was installed as python3 rather than python. Creating symlink."
|
||||
ln -sf /usr/bin/python3 /usr/bin/python
|
||||
sudo ln -sf /usr/bin/python3 /usr/bin/python
|
||||
fi
|
||||
|
||||
# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
|
||||
# To install GCC from source can take hours to compile.
|
||||
#This configuration enables multilib to target many flavors of RISC-V.
|
||||
# This configuration enables multilib to target many flavors of RISC-V.
|
||||
# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well.
|
||||
# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
|
||||
# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
|
||||
@ -68,10 +68,11 @@ fi
|
||||
cd $RISCV
|
||||
git clone https://github.com/riscv/riscv-gnu-toolchain
|
||||
cd riscv-gnu-toolchain
|
||||
git checkout 2023.01.31
|
||||
./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
|
||||
# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249)
|
||||
git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
|
||||
./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
|
||||
#./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
|
||||
make -j ${NUM_THREADS}
|
||||
make install
|
||||
|
||||
# elf2hex (https://github.com/sifive/elf2hex)
|
||||
#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation.
|
||||
@ -112,6 +113,23 @@ cd ../arch_test_target/spike/device
|
||||
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
|
||||
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
|
||||
# Wally needs Verilator 5.0 or later.
|
||||
# Verilator needs to be built from scratch to get the latest version
|
||||
# apt-get install verilator installs version 4.028 as of 6/8/23
|
||||
sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g
|
||||
sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error)
|
||||
cd $RISCV
|
||||
git clone https://github.com/verilator/verilator # Only first time
|
||||
unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
|
||||
unset VERILATOR_ROOT # For bash
|
||||
cd verilator
|
||||
git pull # Make sure git repository is up-to-date
|
||||
git checkout master # Use development branch (e.g. recent bug fixes)
|
||||
autoconf # Create ./configure script
|
||||
./configure # Configure and create Makefile
|
||||
make -j NUM_THREADS # Build Verilator itself (if error, try just 'make')
|
||||
sudo make install
|
||||
|
||||
# Sail (https://github.com/riscv/sail-riscv)
|
||||
# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which
|
||||
# is an object-oriented extension of ML, which in turn is a functional programming
|
||||
@ -131,22 +149,19 @@ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
#pip3 install chardet==3.0.4
|
||||
#pip3 install urllib3==1.22
|
||||
|
||||
cd $RISCV
|
||||
opam init -y --disable-sandboxing
|
||||
opam switch create ocaml-base-compiler.4.06.1
|
||||
opam switch create ocaml-base-compiler.4.08.0
|
||||
opam install sail -y
|
||||
|
||||
eval $(opam config env)
|
||||
git clone https://github.com/riscv/sail-riscv.git
|
||||
cd sail-riscv
|
||||
# Current bug in Sail - use hash that works for Wally
|
||||
# (may remove later if Sail is ever fixed)
|
||||
git checkout 4d05aa1698a0003a4f6f99e1380c743711c32052
|
||||
make -j ${NUM_THREADS}
|
||||
ARCH=RV32 make -j ${NUM_THREADS}
|
||||
ARCH=RV64 make -j ${NUM_THREADS}
|
||||
ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
|
||||
ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
|
||||
|
||||
pip3 install testresources
|
||||
pip3 install riscof --ignore-installed PyYAML
|
||||
sudo pip3 install testresources
|
||||
pip3 install git+https://github.com/riscv/riscof.git
|
||||
|
||||
|
||||
163
config/buildroot/config.vh
Normal file
163
config/buildroot/config.vh
Normal file
@ -0,0 +1,163 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 1;
|
||||
localparam QEMU = 0;
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
localparam MISA = (32'h0014112D);
|
||||
localparam ZICSR_SUPPORTED = 1;
|
||||
localparam ZIFENCEI_SUPPORTED = 1;
|
||||
localparam ZICNTR_SUPPORTED = 1;
|
||||
localparam ZIHPM_SUPPORTED = 1;
|
||||
localparam COUNTERS = 12'd32;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 1;
|
||||
localparam ICACHE_SUPPORTED = 1;
|
||||
localparam VIRTMEM_SUPPORTED = 1;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
|
||||
localparam BIGENDIAN_SUPPORTED = 1;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd32;
|
||||
localparam DTLB_ENTRIES = 32'd32;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 1;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd16;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h00001FFF;
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h00001FFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000 ;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd64;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 0;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd0;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd53;
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -132,6 +132,7 @@
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BPRED_NUM_LHR 6
|
||||
`define BTB_SIZE 10
|
||||
|
||||
|
||||
|
||||
175
config/fpga/config.vh
Normal file
175
config/fpga/config.vh
Normal file
@ -0,0 +1,175 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 1;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
|
||||
localparam ZICSR_SUPPORTED = 1;
|
||||
localparam ZIFENCEI_SUPPORTED = 1;
|
||||
localparam COUNTERS = 12'd32;
|
||||
localparam ZICNTR_SUPPORTED = 1;
|
||||
localparam ZIHPM_SUPPORTED = 1;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 1;
|
||||
localparam ICACHE_SUPPORTED = 1;
|
||||
localparam VIRTMEM_SUPPORTED = 1;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||
localparam BIGENDIAN_SUPPORTED = 1;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd32;
|
||||
localparam DTLB_ENTRIES = 32'd32;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 1;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd16;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd64;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Physical Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h00001FFF;
|
||||
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h00001FFF;
|
||||
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
|
||||
localparam EXT_MEM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
|
||||
localparam CLINT_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
|
||||
localparam GPIO_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
|
||||
localparam UART_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
|
||||
localparam PLIC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
|
||||
localparam SDC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 0;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd0;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd53;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd12;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 1;
|
||||
localparam ZBB_SUPPORTED = 1;
|
||||
localparam ZBC_SUPPORTED = 1;
|
||||
localparam ZBS_SUPPORTED = 1;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -141,6 +141,7 @@
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 12
|
||||
`define BPRED_NUM_LHR 6
|
||||
`define BTB_SIZE 10
|
||||
|
||||
|
||||
|
||||
164
config/rv32e/config.vh
Normal file
164
config/rv32e/config.vh
Normal file
@ -0,0 +1,164 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd32;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// E
|
||||
localparam MISA = (32'h00000010);
|
||||
localparam ZICSR_SUPPORTED = 0;
|
||||
localparam ZIFENCEI_SUPPORTED = 0;
|
||||
localparam COUNTERS = 12'd0;
|
||||
localparam ZICNTR_SUPPORTED = 0;
|
||||
localparam ZIHPM_SUPPORTED = 0;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 0;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 0;
|
||||
localparam ICACHE_SUPPORTED = 0;
|
||||
localparam VIRTMEM_SUPPORTED = 0;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 0;
|
||||
localparam BIGENDIAN_SUPPORTED = 0;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd0;
|
||||
localparam DTLB_ENTRIES = 32'd0;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd1;
|
||||
localparam IDIV_ON_FPU = 0;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd0;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 0;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'd4;
|
||||
localparam DIVCOPIES = 32'd4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
|
||||
178
config/rv32e/rv32e-config.vh
Normal file
178
config/rv32e/rv32e-config.vh
Normal file
@ -0,0 +1,178 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam PA_BITS = 34;
|
||||
//localparam AHBW = 32;
|
||||
//localparam XLEN = 32;
|
||||
//localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
|
||||
////localparam BUS_SUPPORTED = 1'b1;
|
||||
//localparam ZICSR_SUPPORTED = 1'b0;
|
||||
localparam M_SUPPORTED = 1'b0;
|
||||
localparam F_SUPPORTED = 1'b0;
|
||||
//localparam ZMMUL_SUPPORTED = 1'b0;
|
||||
//localparam F_SUPPORTED = 1'b0;
|
||||
//localparam PMP_ENTRIES = 0;
|
||||
localparam LLEN = 32;
|
||||
//localparam FPGA = 1'b0;
|
||||
//localparam QEMU = 1'b0;
|
||||
// //VPN_SEGMENT_BITS: (LLEN == 32 ? 10 : 9),
|
||||
// `include "test-shared.vh"
|
||||
localparam FLEN = 32;
|
||||
|
||||
`include "test-shared.vh"
|
||||
|
||||
|
||||
|
||||
// include shared configuration
|
||||
//`include "wally-shared.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// E
|
||||
localparam MISA = (32'h00000010);
|
||||
localparam ZICSR_SUPPORTED = 0;
|
||||
localparam ZIFENCEI_SUPPORTED = 0;
|
||||
localparam COUNTERS = 0;
|
||||
localparam ZICOUNTERS_SUPPORTED = 0;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 0;
|
||||
localparam ICACHE_SUPPORTED = 0;
|
||||
localparam VIRTMEM_SUPPORTED = 0;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 0;
|
||||
localparam BIGENDIAN_SUPPORTED = 0;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 0;
|
||||
localparam DTLB_ENTRIES = 0;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 4096;
|
||||
localparam DCACHE_LINELENINBITS = 512;
|
||||
localparam ICACHE_NUMWAYS = 4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 4096;
|
||||
localparam ICACHE_LINELENINBITS = 512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 1;
|
||||
localparam IDIV_ON_FPU = 0;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 0;
|
||||
|
||||
// Address space
|
||||
localparam RESET_VECTOR = 32'h80000000;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 16;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam DTIM_BASE = 34'h80000000;
|
||||
localparam DTIM_RANGE = 34'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam IROM_BASE = 34'h80000000;
|
||||
localparam IROM_RANGE = 34'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam BOOTROM_BASE = 34'h00001000;
|
||||
localparam BOOTROM_RANGE = 34'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam UNCORE_RAM_BASE = 34'h80000000;
|
||||
localparam UNCORE_RAM_RANGE = 34'h07FFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam EXT_MEM_BASE = 34'h80000000;
|
||||
localparam EXT_MEM_RANGE = 34'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b0;
|
||||
localparam CLINT_BASE = 34'h02000000;
|
||||
localparam CLINT_RANGE = 34'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b0;
|
||||
localparam GPIO_BASE = 34'h10060000;
|
||||
localparam GPIO_RANGE = 34'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b0;
|
||||
localparam UART_BASE = 34'h10000000;
|
||||
localparam UART_RANGE = 34'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b0;
|
||||
localparam PLIC_BASE = 34'h0C000000;
|
||||
localparam PLIC_RANGE = 34'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam SDC_BASE = 34'h00012100;
|
||||
localparam SDC_RANGE = 34'h0000001F;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 3;
|
||||
localparam PLIC_UART_ID = 10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 0;
|
||||
localparam BPRED_TYPE = "BP_GSHARE"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 10;
|
||||
localparam BTB_SIZE = 10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 4;
|
||||
localparam DIVCOPIES = 4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
@ -1,155 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// E
|
||||
`define MISA (32'h00000010)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 0
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 0
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
164
config/rv32gc/config.vh
Normal file
164
config/rv32gc/config.vh
Normal file
@ -0,0 +1,164 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
// `include "wally-shared.vh"
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd32;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
|
||||
localparam ZICSR_SUPPORTED = 1;
|
||||
localparam ZIFENCEI_SUPPORTED = 1;
|
||||
localparam COUNTERS = 12'd32;
|
||||
localparam ZICNTR_SUPPORTED = 1;
|
||||
localparam ZIHPM_SUPPORTED = 1;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 1;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 1;
|
||||
localparam ICACHE_SUPPORTED = 1;
|
||||
localparam VIRTMEM_SUPPORTED = 1;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||
localparam BIGENDIAN_SUPPORTED = 1;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd32;
|
||||
localparam DTLB_ENTRIES = 32'd32;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 1;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd16;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd16;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'd4;
|
||||
localparam DIVCOPIES = 32'd4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 1;
|
||||
localparam ZBB_SUPPORTED = 1;
|
||||
localparam ZBC_SUPPORTED = 1;
|
||||
localparam ZBS_SUPPORTED = 1;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -1,154 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 1
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 16
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 1
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 1
|
||||
`define ZBB_SUPPORTED 1
|
||||
`define ZBC_SUPPORTED 1
|
||||
`define ZBS_SUPPORTED 1
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
163
config/rv32i/config.vh
Normal file
163
config/rv32i/config.vh
Normal file
@ -0,0 +1,163 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd32;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// I
|
||||
localparam MISA = (32'h00000104);
|
||||
localparam ZICSR_SUPPORTED = 0;
|
||||
localparam ZIFENCEI_SUPPORTED = 0;
|
||||
localparam COUNTERS = 0;
|
||||
localparam ZICNTR_SUPPORTED = 0;
|
||||
localparam ZIHPM_SUPPORTED = 0;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 0;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 0;
|
||||
localparam DCACHE_SUPPORTED = 0;
|
||||
localparam ICACHE_SUPPORTED = 0;
|
||||
localparam VIRTMEM_SUPPORTED = 0;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||
localparam BIGENDIAN_SUPPORTED = 0;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd32;
|
||||
localparam DTLB_ENTRIES = 32'd32;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 0;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd0;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
localparam DTIM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 0;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -1,155 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// I
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
162
config/rv32imc/config.vh
Normal file
162
config/rv32imc/config.vh
Normal file
@ -0,0 +1,162 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd32;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
|
||||
localparam ZICSR_SUPPORTED = 1;
|
||||
localparam ZIFENCEI_SUPPORTED = 1;
|
||||
localparam COUNTERS = 12'd32;
|
||||
localparam ZICNTR_SUPPORTED = 1;
|
||||
localparam ZIHPM_SUPPORTED = 1;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 0;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 0;
|
||||
localparam ICACHE_SUPPORTED = 0;
|
||||
localparam VIRTMEM_SUPPORTED = 0;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||
localparam BIGENDIAN_SUPPORTED = 0;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd0;
|
||||
localparam DTLB_ENTRIES = 32'd0;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd2;
|
||||
localparam IDIV_ON_FPU = 0;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd0;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h80000000;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
localparam DTIM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd32;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 0;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -1,154 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 2
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
165
config/rv64fpquad/config.vh
Normal file
165
config/rv64fpquad/config.vh
Normal file
@ -0,0 +1,165 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
|
||||
localparam ZICSR_SUPPORTED = 1;
|
||||
localparam ZIFENCEI_SUPPORTED = 1;
|
||||
localparam COUNTERS = 12'd32;
|
||||
localparam ZICNTR_SUPPORTED = 1;
|
||||
localparam ZIHPM_SUPPORTED = 1;
|
||||
localparam ZFH_SUPPORTED = 1;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 1;
|
||||
localparam ICACHE_SUPPORTED = 1;
|
||||
localparam VIRTMEM_SUPPORTED = 1;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ;
|
||||
localparam BIGENDIAN_SUPPORTED = 1;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd32;
|
||||
localparam DTLB_ENTRIES = 32'd32;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 1;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd16;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd64;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -1,157 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 1
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
168
config/rv64gc/config.vh
Normal file
168
config/rv64gc/config.vh
Normal file
@ -0,0 +1,168 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
// `include "wally-shared.vh"
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
|
||||
localparam ZICSR_SUPPORTED = 1;
|
||||
localparam ZIFENCEI_SUPPORTED = 1;
|
||||
localparam COUNTERS = 12'd32;
|
||||
localparam ZICNTR_SUPPORTED = 1;
|
||||
localparam ZIHPM_SUPPORTED = 1;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 1;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 1;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 1;
|
||||
localparam DCACHE_SUPPORTED = 1;
|
||||
localparam ICACHE_SUPPORTED = 1;
|
||||
localparam VIRTMEM_SUPPORTED = 1;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||
localparam BIGENDIAN_SUPPORTED = 1;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd32;
|
||||
localparam DTLB_ENTRIES = 32'd32;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 1;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd16;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = 32'd64;
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Physical Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
localparam DTIM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder;
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 1;
|
||||
localparam ZBB_SUPPORTED = 1;
|
||||
localparam ZBC_SUPPORTED = 1;
|
||||
localparam ZBS_SUPPORTED = 1;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -1,157 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 1
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physical Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 1
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 1
|
||||
`define ZBB_SUPPORTED 1
|
||||
`define ZBC_SUPPORTED 1
|
||||
`define ZBS_SUPPORTED 1
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
165
config/rv64i/config.vh
Normal file
165
config/rv64i/config.vh
Normal file
@ -0,0 +1,165 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
localparam FPGA = 0;
|
||||
localparam QEMU = 0;
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
localparam XLEN = 32'd64;
|
||||
|
||||
// IEEE 754 compliance
|
||||
localparam IEEE754 = 0;
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
localparam MISA = (32'h00000104);
|
||||
localparam ZICSR_SUPPORTED = 0;
|
||||
localparam ZIFENCEI_SUPPORTED = 0;
|
||||
localparam COUNTERS = 0;
|
||||
localparam ZICNTR_SUPPORTED = 0;
|
||||
localparam ZIHPM_SUPPORTED = 0;
|
||||
localparam ZFH_SUPPORTED = 0;
|
||||
localparam SSTC_SUPPORTED = 0;
|
||||
localparam ZICBOM_SUPPORTED = 0;
|
||||
localparam ZICBOZ_SUPPORTED = 0;
|
||||
localparam ZICBOP_SUPPORTED = 0;
|
||||
localparam SVPBMT_SUPPORTED = 0;
|
||||
localparam SVINVAL_SUPPORTED = 0;
|
||||
|
||||
// LSU microarchitectural Features
|
||||
localparam BUS_SUPPORTED = 0;
|
||||
localparam DCACHE_SUPPORTED = 0;
|
||||
localparam ICACHE_SUPPORTED = 0;
|
||||
localparam VIRTMEM_SUPPORTED = 0;
|
||||
localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
|
||||
localparam BIGENDIAN_SUPPORTED = 0;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
localparam ITLB_ENTRIES = 32'd0;
|
||||
localparam DTLB_ENTRIES = 32'd0;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
localparam DCACHE_NUMWAYS = 32'd4;
|
||||
localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam DCACHE_LINELENINBITS = 32'd512;
|
||||
localparam ICACHE_NUMWAYS = 32'd4;
|
||||
localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
|
||||
localparam ICACHE_LINELENINBITS = 32'd512;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
localparam IDIV_BITSPERCYCLE = 32'd4;
|
||||
localparam IDIV_ON_FPU = 0;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
localparam PMP_ENTRIES = 32'd0;
|
||||
|
||||
// Address space
|
||||
localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
|
||||
|
||||
// Bus Interface width
|
||||
localparam AHBW = (XLEN);
|
||||
|
||||
// WFI Timeout Wait
|
||||
localparam WFI_TIMEOUT_BIT = 32'd16;
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
localparam DTIM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] DTIM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;
|
||||
localparam IROM_SUPPORTED = 1'b1;
|
||||
localparam logic [63:0] IROM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
|
||||
localparam BOOTROM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
|
||||
localparam UNCORE_RAM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
|
||||
localparam EXT_MEM_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
|
||||
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;
|
||||
localparam CLINT_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] CLINT_BASE = 64'h02000000;
|
||||
localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
|
||||
localparam GPIO_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] GPIO_BASE = 64'h10060000;
|
||||
localparam logic [63:0] GPIO_RANGE = 64'h000000FF;
|
||||
localparam UART_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] UART_BASE = 64'h10000000;
|
||||
localparam logic [63:0] UART_RANGE = 64'h00000007;
|
||||
localparam PLIC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
|
||||
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
|
||||
localparam SDC_SUPPORTED = 1'b0;
|
||||
localparam logic [63:0] SDC_BASE = 64'h00012100;
|
||||
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
localparam GPIO_LOOPBACK_TEST = 1;
|
||||
|
||||
// Hardware configuration
|
||||
localparam UART_PRESCALE = 32'd1;
|
||||
|
||||
// Interrupt configuration
|
||||
localparam PLIC_NUM_SRC = 32'd10;
|
||||
// comment out the following if >=32 sources
|
||||
localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
|
||||
localparam PLIC_GPIO_ID = 32'd3;
|
||||
localparam PLIC_UART_ID = 32'd10;
|
||||
|
||||
localparam BPRED_SUPPORTED = 0;
|
||||
localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
||||
// FPU division architecture
|
||||
localparam RADIX = 32'h4;
|
||||
localparam DIVCOPIES = 32'h4;
|
||||
|
||||
// bit manipulation
|
||||
localparam ZBA_SUPPORTED = 0;
|
||||
localparam ZBB_SUPPORTED = 0;
|
||||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
`include "test-shared.vh"
|
||||
@ -1,157 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW (`XLEN)
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
3
config/shared/BranchPredictorType.vh
Normal file
3
config/shared/BranchPredictorType.vh
Normal file
@ -0,0 +1,3 @@
|
||||
typedef enum logic[3:0] {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC,
|
||||
BP_GLOBAL_BASIC, BP_LOCAL_BASIC, BP_LOCAL_AHEAD, BP_LOCAL_REPAIR} BranchPredictorType;
|
||||
|
||||
175
config/shared/parameter-defs.vh
Normal file
175
config/shared/parameter-defs.vh
Normal file
@ -0,0 +1,175 @@
|
||||
|
||||
// Populate parameter structure with values specific to the current configuration
|
||||
|
||||
parameter cvw_t P = '{
|
||||
FPGA : FPGA,
|
||||
QEMU : QEMU,
|
||||
XLEN : XLEN,
|
||||
IEEE754 : IEEE754,
|
||||
MISA : MISA,
|
||||
AHBW : AHBW,
|
||||
ZICSR_SUPPORTED : ZICSR_SUPPORTED,
|
||||
ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED,
|
||||
COUNTERS : COUNTERS,
|
||||
ZICNTR_SUPPORTED : ZICNTR_SUPPORTED,
|
||||
ZIHPM_SUPPORTED : ZIHPM_SUPPORTED,
|
||||
ZFH_SUPPORTED : ZFH_SUPPORTED,
|
||||
SSTC_SUPPORTED : SSTC_SUPPORTED,
|
||||
VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
|
||||
VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
|
||||
BIGENDIAN_SUPPORTED : BIGENDIAN_SUPPORTED,
|
||||
SVADU_SUPPORTED : SVADU_SUPPORTED,
|
||||
ZMMUL_SUPPORTED : ZMMUL_SUPPORTED,
|
||||
ZICBOM_SUPPORTED : ZICBOM_SUPPORTED,
|
||||
ZICBOZ_SUPPORTED : ZICBOZ_SUPPORTED,
|
||||
ZICBOP_SUPPORTED : ZICBOP_SUPPORTED,
|
||||
SVPBMT_SUPPORTED : SVPBMT_SUPPORTED,
|
||||
SVINVAL_SUPPORTED : SVINVAL_SUPPORTED,
|
||||
BUS_SUPPORTED : BUS_SUPPORTED,
|
||||
DCACHE_SUPPORTED : DCACHE_SUPPORTED,
|
||||
ICACHE_SUPPORTED : ICACHE_SUPPORTED,
|
||||
ITLB_ENTRIES : ITLB_ENTRIES,
|
||||
DTLB_ENTRIES : DTLB_ENTRIES,
|
||||
DCACHE_NUMWAYS : DCACHE_NUMWAYS,
|
||||
DCACHE_WAYSIZEINBYTES : DCACHE_WAYSIZEINBYTES,
|
||||
DCACHE_LINELENINBITS : DCACHE_LINELENINBITS,
|
||||
ICACHE_NUMWAYS : ICACHE_NUMWAYS,
|
||||
ICACHE_WAYSIZEINBYTES : ICACHE_WAYSIZEINBYTES,
|
||||
ICACHE_LINELENINBITS : ICACHE_LINELENINBITS,
|
||||
IDIV_BITSPERCYCLE : IDIV_BITSPERCYCLE,
|
||||
IDIV_ON_FPU : IDIV_ON_FPU,
|
||||
PMP_ENTRIES : PMP_ENTRIES,
|
||||
RESET_VECTOR : RESET_VECTOR,
|
||||
WFI_TIMEOUT_BIT : WFI_TIMEOUT_BIT,
|
||||
DTIM_SUPPORTED : DTIM_SUPPORTED,
|
||||
DTIM_BASE : DTIM_BASE,
|
||||
DTIM_RANGE : DTIM_RANGE,
|
||||
IROM_SUPPORTED : IROM_SUPPORTED,
|
||||
IROM_BASE : IROM_BASE,
|
||||
IROM_RANGE : IROM_RANGE,
|
||||
BOOTROM_SUPPORTED : BOOTROM_SUPPORTED,
|
||||
BOOTROM_BASE : BOOTROM_BASE,
|
||||
BOOTROM_RANGE : BOOTROM_RANGE,
|
||||
UNCORE_RAM_SUPPORTED : UNCORE_RAM_SUPPORTED,
|
||||
UNCORE_RAM_BASE : UNCORE_RAM_BASE,
|
||||
UNCORE_RAM_RANGE : UNCORE_RAM_RANGE,
|
||||
EXT_MEM_SUPPORTED : EXT_MEM_SUPPORTED,
|
||||
EXT_MEM_BASE : EXT_MEM_BASE,
|
||||
EXT_MEM_RANGE : EXT_MEM_RANGE,
|
||||
CLINT_SUPPORTED : CLINT_SUPPORTED,
|
||||
CLINT_BASE : CLINT_BASE,
|
||||
CLINT_RANGE : CLINT_RANGE,
|
||||
GPIO_SUPPORTED : GPIO_SUPPORTED,
|
||||
GPIO_BASE : GPIO_BASE,
|
||||
GPIO_RANGE : GPIO_RANGE,
|
||||
UART_SUPPORTED : UART_SUPPORTED,
|
||||
UART_BASE : UART_BASE,
|
||||
UART_RANGE : UART_RANGE,
|
||||
PLIC_SUPPORTED : PLIC_SUPPORTED,
|
||||
PLIC_BASE : PLIC_BASE,
|
||||
PLIC_RANGE : PLIC_RANGE,
|
||||
SDC_SUPPORTED : SDC_SUPPORTED,
|
||||
SDC_BASE : SDC_BASE,
|
||||
SDC_RANGE : SDC_RANGE,
|
||||
GPIO_LOOPBACK_TEST : GPIO_LOOPBACK_TEST,
|
||||
UART_PRESCALE : UART_PRESCALE ,
|
||||
PLIC_NUM_SRC : PLIC_NUM_SRC,
|
||||
PLIC_NUM_SRC_LT_32 : PLIC_NUM_SRC_LT_32,
|
||||
PLIC_GPIO_ID : PLIC_GPIO_ID,
|
||||
PLIC_UART_ID : PLIC_UART_ID,
|
||||
BPRED_SUPPORTED : BPRED_SUPPORTED,
|
||||
/* verilator lint_off ENUMVALUE */
|
||||
// *** definitely need to fix this.
|
||||
// it thinks we are casting from the enum type to BPRED_TYPE.
|
||||
BPRED_TYPE : BPRED_TYPE,
|
||||
/* verilator lint_on ENUMVALUE */
|
||||
BPRED_SIZE : BPRED_SIZE,
|
||||
BPRED_NUM_LHR : BPRED_NUM_LHR,
|
||||
BTB_SIZE : BTB_SIZE,
|
||||
RADIX : RADIX,
|
||||
DIVCOPIES : DIVCOPIES,
|
||||
ZBA_SUPPORTED : ZBA_SUPPORTED,
|
||||
ZBB_SUPPORTED : ZBB_SUPPORTED,
|
||||
ZBC_SUPPORTED : ZBC_SUPPORTED,
|
||||
ZBS_SUPPORTED : ZBS_SUPPORTED,
|
||||
USE_SRAM : USE_SRAM,
|
||||
M_MODE : M_MODE,
|
||||
S_MODE : S_MODE,
|
||||
U_MODE : U_MODE,
|
||||
VPN_SEGMENT_BITS : VPN_SEGMENT_BITS,
|
||||
VPN_BITS : VPN_BITS,
|
||||
PPN_BITS : PPN_BITS,
|
||||
PA_BITS : PA_BITS,
|
||||
SVMODE_BITS : SVMODE_BITS,
|
||||
ASID_BASE : ASID_BASE,
|
||||
ASID_BITS : ASID_BITS,
|
||||
NO_TRANSLATE : NO_TRANSLATE,
|
||||
SV32 : SV32,
|
||||
SV39 : SV39,
|
||||
SV48 : SV48,
|
||||
A_SUPPORTED : A_SUPPORTED,
|
||||
B_SUPPORTED : B_SUPPORTED,
|
||||
C_SUPPORTED : C_SUPPORTED,
|
||||
D_SUPPORTED : D_SUPPORTED,
|
||||
E_SUPPORTED : E_SUPPORTED,
|
||||
F_SUPPORTED : F_SUPPORTED,
|
||||
I_SUPPORTED : I_SUPPORTED,
|
||||
M_SUPPORTED : M_SUPPORTED,
|
||||
Q_SUPPORTED : Q_SUPPORTED,
|
||||
S_SUPPORTED : S_SUPPORTED,
|
||||
U_SUPPORTED : U_SUPPORTED,
|
||||
LOG_XLEN : LOG_XLEN,
|
||||
PMPCFG_ENTRIES : PMPCFG_ENTRIES,
|
||||
Q_LEN : Q_LEN,
|
||||
Q_NE : Q_NE,
|
||||
Q_NF : Q_NF,
|
||||
Q_BIAS : Q_BIAS,
|
||||
Q_FMT : Q_FMT,
|
||||
D_LEN : D_LEN,
|
||||
D_NE : D_NE,
|
||||
D_NF : D_NF,
|
||||
D_BIAS : D_BIAS,
|
||||
D_FMT : D_FMT,
|
||||
S_LEN : S_LEN,
|
||||
S_NE : S_NE,
|
||||
S_NF : S_NF,
|
||||
S_BIAS : S_BIAS,
|
||||
S_FMT : S_FMT,
|
||||
H_LEN : H_LEN,
|
||||
H_NE : H_NE,
|
||||
H_NF : H_NF,
|
||||
H_BIAS : H_BIAS,
|
||||
H_FMT : H_FMT,
|
||||
FLEN : FLEN,
|
||||
NE : NE ,
|
||||
NF : NF ,
|
||||
FMT : FMT ,
|
||||
BIAS : BIAS,
|
||||
FPSIZES : FPSIZES,
|
||||
FMTBITS : FMTBITS,
|
||||
LEN1 : LEN1 ,
|
||||
NE1 : NE1 ,
|
||||
NF1 : NF1 ,
|
||||
FMT1 : FMT1 ,
|
||||
BIAS1 : BIAS1,
|
||||
LEN2 : LEN2 ,
|
||||
NE2 : NE2 ,
|
||||
NF2 : NF2 ,
|
||||
FMT2 : FMT2 ,
|
||||
BIAS2 : BIAS2,
|
||||
CVTLEN : CVTLEN,
|
||||
LLEN : LLEN,
|
||||
LOGCVTLEN : LOGCVTLEN,
|
||||
NORMSHIFTSZ : NORMSHIFTSZ,
|
||||
LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
|
||||
CORRSHIFTSZ : CORRSHIFTSZ,
|
||||
DIVN : DIVN,
|
||||
LOGR : LOGR,
|
||||
RK : RK,
|
||||
LOGRK : LOGRK,
|
||||
FPDUR : FPDUR,
|
||||
DURLEN : DURLEN,
|
||||
DIVb : DIVb,
|
||||
DIVBLEN : DIVBLEN,
|
||||
DIVa : DIVa
|
||||
};
|
||||
119
config/shared/test-shared.vh
Normal file
119
config/shared/test-shared.vh
Normal file
@ -0,0 +1,119 @@
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
localparam M_MODE = (2'b11);
|
||||
localparam S_MODE = (2'b01);
|
||||
localparam U_MODE = (2'b00);
|
||||
|
||||
// Virtual Memory Constants
|
||||
localparam VPN_SEGMENT_BITS = (XLEN == 32 ? 32'd10 : 32'd9);
|
||||
localparam VPN_BITS = (XLEN==32 ? (2*VPN_SEGMENT_BITS) : (4*VPN_SEGMENT_BITS));
|
||||
localparam PPN_BITS = (XLEN==32 ? 32'd22 : 32'd44);
|
||||
localparam PA_BITS = (XLEN==32 ? 32'd34 : 32'd56);
|
||||
localparam SVMODE_BITS = (XLEN==32 ? 32'd1 : 32'd4);
|
||||
localparam ASID_BASE = (XLEN==32 ? 32'd22 : 32'd44);
|
||||
localparam ASID_BITS = (XLEN==32 ? 32'd9 : 32'd16);
|
||||
|
||||
// constants to check SATP_MODE against
|
||||
// defined in Table 4.3 of the privileged spec
|
||||
localparam NO_TRANSLATE = 4'd0;
|
||||
localparam SV32 = 4'd1;
|
||||
localparam SV39 = 4'd8;
|
||||
localparam SV48 = 4'd9;
|
||||
|
||||
// macros to define supported modes
|
||||
localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
|
||||
localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
|
||||
localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
|
||||
localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
|
||||
localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
|
||||
localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
|
||||
localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
|
||||
localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
|
||||
localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
|
||||
localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);
|
||||
localparam U_SUPPORTED = ((MISA >> 20) % 2 == 1);
|
||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
localparam PMPCFG_ENTRIES = (PMP_ENTRIES/32'd8);
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
// Lim: I've made some of these 64 bit to avoid width warnings.
|
||||
// If errors crop up, try downsizing back to 32.
|
||||
localparam Q_LEN = 32'd128;
|
||||
localparam Q_NE = 32'd15;
|
||||
localparam Q_NF = 32'd112;
|
||||
localparam Q_BIAS = 32'd16383;
|
||||
localparam Q_FMT = 2'd3;
|
||||
localparam D_LEN = 32'd64;
|
||||
localparam D_NE = 32'd11;
|
||||
localparam D_NF = 32'd52;
|
||||
localparam D_BIAS = 32'd1023;
|
||||
localparam D_FMT = 2'd1;
|
||||
localparam S_LEN = 32'd32;
|
||||
localparam S_NE = 32'd8;
|
||||
localparam S_NF = 32'd23;
|
||||
localparam S_BIAS = 32'd127;
|
||||
localparam S_FMT = 2'd0;
|
||||
localparam H_LEN = 32'd16;
|
||||
localparam H_NE = 32'd5;
|
||||
localparam H_NF = 32'd10;
|
||||
localparam H_BIAS = 32'd15;
|
||||
localparam H_FMT = 2'd2;
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN);
|
||||
localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE);
|
||||
localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF);
|
||||
localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0);
|
||||
localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS);
|
||||
/* Delete once tested dh 10/10/22
|
||||
|
||||
localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : F_SUPPORTED ? S_LEN : H_LEN);
|
||||
localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : F_SUPPORTED ? S_NE : H_NE);
|
||||
localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : F_SUPPORTED ? S_NF : H_NF);
|
||||
localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : F_SUPPORTED ? 2'd0 : 2'd2);
|
||||
localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : F_SUPPORTED ? S_BIAS : H_BIAS);*/
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
localparam FPSIZES = ((32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED));
|
||||
localparam FMTBITS = ((32)'(FPSIZES>=3)+1);
|
||||
localparam LEN1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_LEN : (F_SUPPORTED & (FLEN != S_LEN)) ? S_LEN : H_LEN);
|
||||
localparam NE1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NE : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NE : H_NE);
|
||||
localparam NF1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NF : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NF : H_NF);
|
||||
localparam FMT1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? 2'd1 : (F_SUPPORTED & (FLEN != S_LEN)) ? 2'd0 : 2'd2);
|
||||
localparam BIAS1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_BIAS : (F_SUPPORTED & (FLEN != S_LEN)) ? S_BIAS : H_BIAS);
|
||||
localparam LEN2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_LEN : H_LEN);
|
||||
localparam NE2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NE : H_NE);
|
||||
localparam NF2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF : H_NF);
|
||||
localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2);
|
||||
localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
|
||||
|
||||
// division constants
|
||||
localparam DIVN = (((NF+2<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
|
||||
localparam LOGR = ($clog2(RADIX)); // r = log(R)
|
||||
localparam RK = (LOGR*DIVCOPIES); // r*k used for intdiv preproc
|
||||
localparam LOGRK = ($clog2(RK)); // log2(r*k)
|
||||
localparam FPDUR = ((DIVN+1+(LOGR*DIVCOPIES))/(LOGR*DIVCOPIES)+(RADIX/4));
|
||||
localparam DURLEN = ($clog2(FPDUR+1));
|
||||
localparam DIVb = (FPDUR*LOGR*DIVCOPIES-1); // canonical fdiv size (b)
|
||||
localparam DIVBLEN = ($clog2(DIVb+1)-1);
|
||||
localparam DIVa = (DIVb+1-XLEN); // used for idiv on fpu
|
||||
|
||||
// largest length in IEU/FPU
|
||||
localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));
|
||||
localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
|
||||
localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
|
||||
localparam NORMSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVb + 1 +NF+1) > (3*NF+6) ? (DIVb + 1 +NF+1) : (3*NF+6)));
|
||||
localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
|
||||
localparam CORRSHIFTSZ = (((CVTLEN+NF+1)>(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+6)) ? (CVTLEN+NF+1) : ((DIVN+1+NF) > (3*NF+4) ? (DIVN+1+NF) : (3*NF+4)));
|
||||
|
||||
|
||||
// Disable spurious Verilator warnings
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
@ -98,7 +98,7 @@
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
@ -125,7 +125,7 @@
|
||||
|
||||
// division constants
|
||||
|
||||
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
|
||||
`define DIVN ((((`NF+2)<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
|
||||
`define LOGR ($clog2(`RADIX)) // r = log(R)
|
||||
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
|
||||
`define LOGRK ($clog2(`RK)) // log2(r*k)
|
||||
|
||||
@ -1,6 +1,29 @@
|
||||
# CORE-V Wally Test Plan
|
||||
# CORE-V Wally Design Verification Test Plan
|
||||
|
||||
CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
|
||||
|
||||
| Functions | Coverage Method | Status |
|
||||
| ----------- | ----------- |----|
|
||||
| Instructions | riscv-arch-test | Pass |
|
||||
| Privileged Unit | wally-riscv-arch-test | Pass |
|
||||
| Virtual Memory | wally-riscv-arch-test | Pass |
|
||||
| PMP | wally-riscv-arch-test | Pass
|
||||
| Peripherals | wally-riscv-arch-test | Pass |
|
||||
| Floating-Point | TestFloat | Pass |
|
||||
| General | Code Coverage | 91% |
|
||||
| General | Boot Linux in Sim | Pass |
|
||||
| General | Boot Linux on FPGA | Pass |
|
||||
|
||||
|
||||
The following performance validation is also run:
|
||||
| Function | Method | Status |
|
||||
| --- | --- | --- |
|
||||
| Overall Performance | embench | Pass|
|
||||
| Overall Performance | coremark | Pass |
|
||||
| Branch Predictor | *** | Pass |
|
||||
| Cache Miss Rate | *** | Pass |
|
||||
|
||||
|
||||
CORE-V Wally is tested in the following ways:
|
||||
|
||||
* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
|
||||
* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
|
||||
|
||||
@ -28,8 +28,8 @@ SECTIONS
|
||||
. = ALIGN(0x1000);
|
||||
.tohost : { *(.tohost) }
|
||||
|
||||
. = ALIGN(0x1000);
|
||||
.text : { *(.text) }
|
||||
/* . = ALIGN(0x1000);
|
||||
.text : { *(.text) } */
|
||||
|
||||
/* data segment */
|
||||
.data : { *(.data) }
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
8
examples/verilog/fulladder/fulladder-batch-coverage.do
Normal file
8
examples/verilog/fulladder/fulladder-batch-coverage.do
Normal file
@ -0,0 +1,8 @@
|
||||
# fulladder-batch-coverage.do
|
||||
# David_Harris@hmc.edu 22 May 2023
|
||||
vlog fulladder.sv
|
||||
vopt +acc work.testbench -o workopt +cover=sbecf
|
||||
vsim workopt -coverage
|
||||
run -all
|
||||
coverage save -instance /testbench/dut fulladder.ucdb
|
||||
quit
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -21,32 +21,32 @@ connect_debug_port u_ila_0/clk [get_nets CPUCLK]
|
||||
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 28 [get_debug_ports u_ila_0/probe6]
|
||||
@ -131,7 +131,7 @@ connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe22]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
|
||||
|
||||
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
|
||||
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
|
||||
|
||||
52
fpga/constraints/vcu-small-debug.xdc
Normal file
52
fpga/constraints/vcu-small-debug.xdc
Normal file
@ -0,0 +1,52 @@
|
||||
create_debug_core u_ila_0 ila
|
||||
|
||||
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
startgroup
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
|
||||
endgroup
|
||||
connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
|
||||
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
|
||||
|
||||
@ -3,9 +3,9 @@ sdc_src := ~/repos/sdc.tar.gz
|
||||
|
||||
# Select the desired board and the all build rules
|
||||
# vcu118
|
||||
#export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
#export board := vcu118
|
||||
export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
export board := vcu118
|
||||
|
||||
# vcu108
|
||||
#export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
@ -13,15 +13,15 @@ sdc_src := ~/repos/sdc.tar.gz
|
||||
#export board := vcu108
|
||||
|
||||
# Arty A7
|
||||
export XILINX_PART := xc7a100tcsg324-1
|
||||
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
export board := ArtyA7
|
||||
#export XILINX_PART := xc7a100tcsg324-1
|
||||
#export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
#export board := ArtyA7
|
||||
|
||||
# for Arty A7 and S7 boards
|
||||
all: FPGA_Arty
|
||||
#all: FPGA_Arty
|
||||
|
||||
# VCU 108 and VCU 118 boards
|
||||
#all: FPGA_VCU
|
||||
all: FPGA_VCU
|
||||
|
||||
FPGA_Arty: PreProcessFiles IP_Arty SDC
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
@ -12,6 +12,17 @@ if {$boardName!="ArtyA7"} {
|
||||
set_property board_part $boardName [current_project]
|
||||
}
|
||||
|
||||
# read package first
|
||||
read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
|
||||
read_verilog -sv ../src/wallypipelinedsocwrapper.sv
|
||||
# then read top level
|
||||
if {$board=="ArtyA7"} {
|
||||
read_verilog {../src/fpgaTopArtyA7.v}
|
||||
} else {
|
||||
read_verilog {../src/fpgaTop.v}
|
||||
}
|
||||
|
||||
# read in ip
|
||||
read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
|
||||
read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
|
||||
read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
|
||||
@ -23,17 +34,13 @@ if {$board=="ArtyA7"} {
|
||||
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
|
||||
}
|
||||
|
||||
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
|
||||
if {$board=="ArtyA7"} {
|
||||
read_verilog {../src/fpgaTopArtyA7.v}
|
||||
} else {
|
||||
read_verilog {../src/fpgaTop.v}
|
||||
}
|
||||
# read in all other rtl
|
||||
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
|
||||
|
||||
read_verilog -sv [glob -type f ../src/sdc/*.sv]
|
||||
|
||||
set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
|
||||
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
|
||||
@ -45,7 +52,6 @@ if {$board=="ArtyA7"} {
|
||||
# define top level
|
||||
set_property top fpgaTop [current_fileset]
|
||||
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
# This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
|
||||
exec mkdir -p reports/
|
||||
@ -76,8 +82,8 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
|
||||
if {$board=="ArtyA7"} {
|
||||
source ../constraints/small-debug.xdc
|
||||
|
||||
} else {
|
||||
source ../constraints/debug4.xdc
|
||||
} else {
|
||||
source ../constraints/vcu-small-debug.xdc
|
||||
}
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -24,8 +24,6 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fpgaTop
|
||||
(input default_250mhz_clk1_0_n,
|
||||
input default_250mhz_clk1_0_p,
|
||||
@ -72,12 +70,12 @@ module fpgaTop
|
||||
|
||||
wire HCLKOpen;
|
||||
wire HRESETnOpen;
|
||||
wire [`AHBW-1:0] HRDATAEXT;
|
||||
wire [64-1:0] HRDATAEXT;
|
||||
wire HREADYEXT;
|
||||
wire HRESPEXT;
|
||||
wire HSELEXT;
|
||||
wire [31:0] HADDR;
|
||||
wire [`AHBW-1:0] HWDATA;
|
||||
wire [64-1:0] HWDATA;
|
||||
wire HWRITE;
|
||||
wire [2:0] HSIZE;
|
||||
wire [2:0] HBURST;
|
||||
@ -211,7 +209,7 @@ module fpgaTop
|
||||
|
||||
|
||||
// wally
|
||||
wallypipelinedsoc wallypipelinedsoc
|
||||
wallypipelinedsocwrapper wallypipelinedsocwrapper
|
||||
(.clk(CPUCLK),
|
||||
.reset_ext(bus_struct_reset),
|
||||
// bus interface
|
||||
|
||||
@ -225,7 +225,7 @@ module fpgaTop
|
||||
.peripheral_aresetn(peripheral_aresetn));
|
||||
|
||||
// wally
|
||||
wallypipelinedsoc wallypipelinedsoc
|
||||
wallypipelinedsocwrapper wallypipelinedsocwrapper
|
||||
(.clk(CPUCLK),
|
||||
.reset_ext(bus_struct_reset),
|
||||
// bus interface
|
||||
|
||||
72
fpga/src/wallypipelinedsocwrapper.sv
Normal file
72
fpga/src/wallypipelinedsocwrapper.sv
Normal file
@ -0,0 +1,72 @@
|
||||
///////////////////////////////////////////
|
||||
// wallypipelinedsocwrapper.sv
|
||||
//
|
||||
// Written: Ross Thompson ross1728@gmail.com 16 June 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,
|
||||
// not system verilog.
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "config.vh"
|
||||
|
||||
import cvw::*;
|
||||
|
||||
module wallypipelinedsocwrapper (
|
||||
input logic clk,
|
||||
input logic reset_ext, // external asynchronous reset pin
|
||||
output logic reset, // reset synchronized to clk to prevent races on release
|
||||
// AHB Interface
|
||||
input logic [64-1:0] HRDATAEXT,
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
output logic HSELEXT,
|
||||
// outputs to external memory, shared with uncore memory
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [64-1:0] HADDR,
|
||||
output logic [64-1:0] HWDATA,
|
||||
output logic [64/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK,
|
||||
output logic HREADY,
|
||||
// I/O Interface
|
||||
input logic TIMECLK, // optional for CLINT MTIME counter
|
||||
input logic [31:0] GPIOIN, // inputs from GPIO
|
||||
output logic [31:0] GPIOOUT, // output values for GPIO
|
||||
output logic [31:0] GPIOEN, // output enables for GPIO
|
||||
input logic UARTSin, // UART serial data input
|
||||
output logic UARTSout, // UART serial data output
|
||||
input logic SDCCmdIn, // SDC Command input
|
||||
output logic SDCCmdOut, // SDC Command output
|
||||
output logic SDCCmdOE, // SDC Command output enable
|
||||
input logic [3:0] SDCDatIn, // SDC data input
|
||||
output logic SDCCLK // SDC clock
|
||||
);
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
wallypipelinedsoc #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
endmodule
|
||||
1
setup.sh
1
setup.sh
@ -17,6 +17,7 @@ echo \$WALLY set to ${WALLY}
|
||||
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server
|
||||
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
|
||||
export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim # Change this for your path to Questa, excluding bin
|
||||
#export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_3/questasim # Change this for your path to Questa, excluding bin
|
||||
export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
|
||||
|
||||
# Path to RISC-V Tools
|
||||
|
||||
56
sim/FPbuild.txt
Normal file
56
sim/FPbuild.txt
Normal file
@ -0,0 +1,56 @@
|
||||
Procedure for Runnning SoftFloat/TestFloat with Wally
|
||||
|
||||
1.) First, compile SoftFloat and TestFloat by going to the addins
|
||||
directory and finding the specific build directory (e.g.,
|
||||
Linux_x86_64-GCC. Currently, we are using v3e of
|
||||
SoftFloat/TestFloat. I am not sure of the order, but I always compile
|
||||
SoftFloat first as I believe TestFloat uses the static library
|
||||
SoftFloat creates.
|
||||
|
||||
2.) Once compiled both, go to the tests/fp directory and run the
|
||||
create_vectors.sh Linux script. In the past, we have automated this,
|
||||
but I believe this has fallen into more of a manual state lately.
|
||||
|
||||
3.) Then, run remove_spaces.sh which will remove spaces from the
|
||||
output and put underscores between vectors (this helps differentiate
|
||||
the vectors that are generated). Again, this can be combined with
|
||||
Step 2.
|
||||
|
||||
4.) TestFloat is run from wally/cvw/sim and sim-testfloat-batch with
|
||||
its respective test. The format is ./sim-testfloat-add add. All of
|
||||
the tests are listed below. This can be augmented or added to for
|
||||
other FP tests given by the great SoftFloat/TestFloat output.
|
||||
|
||||
cvtint - test integer conversion unit (fcvtint)
|
||||
cvtfp - test floating-point conversion unit (fcvtfp)
|
||||
cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
||||
add - test addition
|
||||
fma - test fma
|
||||
mul - test mult with fma
|
||||
sub - test subtraction
|
||||
div - test division
|
||||
sqrt - test square root
|
||||
all - test everything
|
||||
|
||||
4a.) Each test will test all its vectors - if you want to test a
|
||||
subset of the vectors (e.g., only binary16), you should modify the
|
||||
testfloat.do in the sim directory. Change the TEST_SIZE="all" to the
|
||||
specific test you want to run. For example, if you want to run only
|
||||
binary16, you should set this variable to TEST_SIZE="HP".
|
||||
|
||||
4b.) If you want to turn off the generation of wlf files while running
|
||||
sim-testfloat-batch, you can modify testfloat.do in the sim
|
||||
directory. Inside this DO file, modify the WAV file to 0 --> i.e.,
|
||||
set "quietly set WAV 0;"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -18,8 +18,8 @@ all: riscoftests memfiles coveragetests
|
||||
coverage:
|
||||
#make -C ../tests/coverage --jobs
|
||||
#iter-elf.bash --cover --search ../tests/coverage
|
||||
vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
|
||||
# vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log
|
||||
vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log
|
||||
# vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
|
||||
vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
|
||||
vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
|
||||
vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt
|
||||
|
||||
@ -46,18 +46,33 @@ configs = [
|
||||
)
|
||||
]
|
||||
|
||||
# bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
|
||||
# for CurrBPType in bpdType:
|
||||
# for CurrBPSize in bpdSize:
|
||||
# name = CurrBPType+str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
|
||||
# tc = TestCase(
|
||||
# name=name,
|
||||
# variant="rv32gc",
|
||||
# cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
# grepstr="")
|
||||
# configs.append(tc)
|
||||
|
||||
bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic']
|
||||
LHRSize = [4, 8, 10]
|
||||
bpdType = ['local_repair']
|
||||
for CurrBPType in bpdType:
|
||||
for CurrBPSize in bpdSize:
|
||||
name = CurrBPType+str(CurrBPSize)
|
||||
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
|
||||
tc = TestCase(
|
||||
name=name,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
grepstr="")
|
||||
configs.append(tc)
|
||||
for CurrLHRSize in LHRSize:
|
||||
name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
|
||||
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
|
||||
tc = TestCase(
|
||||
name=name,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
grepstr="")
|
||||
configs.append(tc)
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
||||
@ -31,11 +31,14 @@
|
||||
do GetLineNum.do
|
||||
|
||||
# LZA (i<64) statement confuses coverage tool
|
||||
# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working
|
||||
# DH 4/22/23: Exclude all LZAs
|
||||
coverage exclude -srcfile lzc.sv
|
||||
|
||||
# FDIVSQRT has
|
||||
# DH 4/22/23: FDIVSQRT can't go directly from done to busy again
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
|
||||
# DH 4/22/23: The busy->idle transition only occurs if a FlushE occurs while the divider is busy. The flush is caused by a trap or return,
|
||||
# which won't happen while the divider is busy.
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE
|
||||
|
||||
### Exclude D$ states and logic for the I$ instance
|
||||
# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
|
||||
@ -74,7 +77,7 @@ for {set i 0} {$i < $numcacheways} {incr i} {
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
|
||||
# below: flushD can't go high during an icache write b/c of pipeline stall
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
}
|
||||
|
||||
## D$ Exclusions.
|
||||
@ -85,11 +88,18 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
|
||||
set numcacheways 4
|
||||
for {set i 0} {$i < $numcacheways} {incr i} {
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item be 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
|
||||
|
||||
# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
|
||||
# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
}
|
||||
# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
|
||||
|
||||
####################
|
||||
# Unused / illegal peripheral accesses
|
||||
####################
|
||||
|
||||
# Excluding peripherals as sources of instructions for the ifu
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec
|
||||
@ -97,31 +107,134 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
|
||||
|
||||
# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
|
||||
# Excluding so far un-used instruction sources for the ifu
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
|
||||
|
||||
|
||||
#Excluding the bootrom, uncoreran, and clint as sources for the lsu
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
|
||||
|
||||
|
||||
#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
|
||||
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
|
||||
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
|
||||
|
||||
# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1
|
||||
set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/dtimdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
####################
|
||||
# Unused access types due to sharing IFU and LSU logic
|
||||
####################
|
||||
|
||||
## The lsu never executes instructions so 'ExecuteAccessF' will never be 1
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true
|
||||
|
||||
## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM \\| PMPLoadAccessFaultM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
|
||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
# IMMU only makes word-sized accesses
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
|
||||
set line2 [expr $line + 6 ]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
|
||||
|
||||
# No irom
|
||||
set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
|
||||
coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6
|
||||
set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"]
|
||||
coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4
|
||||
|
||||
# Excluding reset and clear for impossible case in the wficountreg in privdec
|
||||
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
|
||||
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
|
||||
|
||||
# TLB not recently used never has all RU bits = 1 because it will then clear all to 0
|
||||
# This is a blunt instrument; perhaps there is a more graceful exclusion
|
||||
coverage exclude -srcfile priorityonehot.sv
|
||||
|
||||
# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#--mpdconsole
|
||||
#--gdbconsole
|
||||
--showoverrides
|
||||
--showcommands
|
||||
#--showoverrides
|
||||
#--showcommands
|
||||
|
||||
# Core settings
|
||||
--override cpu/priv_version=1.12
|
||||
|
||||
@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
|
||||
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
|
||||
#for config in rv64gc; do
|
||||
echo "$config linting..."
|
||||
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
||||
if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
||||
echo "Exiting after $config lint due to errors or warnings"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
@ -3,17 +3,18 @@ quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/co
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/reset
|
||||
add wave -noupdate -expand -group Testbench /testbench/reset_ext
|
||||
add wave -noupdate -expand -group Testbench -radix unsigned /testbench/InstrCountW
|
||||
add wave -noupdate -expand -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
|
||||
add wave -noupdate -expand -group Testbench -radix decimal /testbench/interruptInstrCount
|
||||
add wave -noupdate -expand -group Testbench /testbench/interruptCauseVal
|
||||
add wave -noupdate -expand -group Testbench /testbench/interruptEpcVal
|
||||
add wave -noupdate -expand -group Testbench /testbench/interruptTVal
|
||||
add wave -noupdate -expand -group Testbench /testbench/interruptDesc
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW
|
||||
add wave -noupdate -group Testbench /testbench/reset_ext
|
||||
add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW
|
||||
add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
|
||||
add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount
|
||||
add wave -noupdate -group Testbench /testbench/interruptCauseVal
|
||||
add wave -noupdate -group Testbench /testbench/interruptEpcVal
|
||||
add wave -noupdate -group Testbench /testbench/interruptTVal
|
||||
add wave -noupdate -group Testbench /testbench/interruptDesc
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
@ -30,17 +31,16 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
@ -73,55 +73,12 @@ add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/textW
|
||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
|
||||
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
|
||||
add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCM
|
||||
@ -129,10 +86,6 @@ add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
|
||||
@ -147,7 +100,6 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
|
||||
add wave -noupdate -group alu -divider internals
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
|
||||
@ -165,10 +117,6 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
@ -176,162 +124,149 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNe
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/PAdrM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
|
||||
add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
|
||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
|
||||
@ -344,23 +279,12 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||
add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
||||
add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
|
||||
add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/funct
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/result
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srca
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srcb
|
||||
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/width
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
||||
@ -412,9 +336,10 @@ add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {15300495 ns} 1} {{Cursor 4} {4919381 ns} 1} {{Cursor 5} {4934568 ns} 0}
|
||||
quietly wave cursor active 5
|
||||
WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
configure wave -justifyvalue left
|
||||
@ -429,4 +354,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {4934554 ns} {4934778 ns}
|
||||
WaveRestoreZoom {165196205 ns} {165196487 ns}
|
||||
|
||||
@ -85,7 +85,7 @@ for test in tests64i:
|
||||
configs.append(tc)
|
||||
|
||||
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
|
||||
tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
|
||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
|
||||
for test in tests32gc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
@ -132,15 +132,13 @@ for test in ahbTests:
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
|
||||
if (coverage): # delete all but 64gc tests when running coverage
|
||||
configs = []
|
||||
# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
"arch64zi", "wally64a", "wally64periph", "wally64priv",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]
|
||||
if (fp):
|
||||
tests64gc.append("arch64f")
|
||||
tests64gc.append("arch64d")
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
|
||||
export IMPERAS_TOOLS=$(pwd)/imperas.ic
|
||||
export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
|
||||
export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
|
||||
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
|
||||
export OTHERFLAGS=""
|
||||
|
||||
vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"
|
||||
|
||||
@ -10,6 +10,4 @@
|
||||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
# nowave for 2nd argument supresses wlf files
|
||||
|
||||
vsim -c -do "do testfloat.do rv64fpquad $1 $2"
|
||||
vsim -c -do "do testfloat.do rv64fpquad $1"
|
||||
@ -1 +1 @@
|
||||
vsim -c -do "do wally-batch.do rv32gc wally32priv"
|
||||
vsim -c -do "do wally-batch.do rv64gc wally64priv"
|
||||
|
||||
@ -25,14 +25,18 @@ vlib work
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
# $num = the added words after the call
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
||||
|
||||
vsim -voptargs=+acc work.testbenchfp -G TEST=$2
|
||||
# Change TEST_SIZE to only test certain FP width
|
||||
# values are QP, DP, SP, HP
|
||||
vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"
|
||||
|
||||
# Determine if nowave argument is provided
|
||||
# this removes any output to a wlf or wave window to reduce
|
||||
# disk space.
|
||||
if {($argc > 2) && ($3 eq "nowave")} {
|
||||
# Set WAV variable to avoid having any output to wave (to limit disk space)
|
||||
quietly set WAV 1;
|
||||
|
||||
# Determine if nowave argument is provided this removes any output to
|
||||
# a wlf or wave window to reduce disk space.
|
||||
if {$WAV eq 0} {
|
||||
puts "No wave output is selected"
|
||||
} else {
|
||||
puts "wave output is selected"
|
||||
|
||||
22
sim/verilate
Executable file
22
sim/verilate
Executable file
@ -0,0 +1,22 @@
|
||||
#!/bin/bash
|
||||
# simulate with Verilator
|
||||
|
||||
export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)/..
|
||||
#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
|
||||
for config in rv64gc; do
|
||||
echo "$config simulating..."
|
||||
if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
|
||||
echo "Exiting after $config lint due to errors or warnings"
|
||||
exit 1
|
||||
fi
|
||||
done
|
||||
echo "All lints run with no errors or warnings"
|
||||
|
||||
# --lint-only just runs lint rather than trying to compile and simulate
|
||||
# -I points to the include directory where files such as `include wally-config.vh are found
|
||||
|
||||
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
|
||||
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
|
||||
@ -59,7 +59,7 @@ if {$argc >= 3} {
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32imc rv32imc
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
if { $coverage } {
|
||||
echo "wally-batch buildroot coverage"
|
||||
@ -88,7 +88,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "ahb"} {
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
|
||||
@ -112,7 +112,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
# **** fix this so we can pass any number of +defines.
|
||||
# only allows 3 right now
|
||||
|
||||
vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
|
||||
vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt
|
||||
@ -126,7 +126,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
# power off -r /dut/core/*
|
||||
|
||||
} else {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
if {$coverage} {
|
||||
|
||||
@ -29,20 +29,21 @@ vlog +incdir+../config/$1 \
|
||||
+define+USE_IMPERAS_DV \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
|
||||
\
|
||||
+define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
|
||||
+define+COVER_RV64I \
|
||||
+define+COVER_RV64C \
|
||||
+define+COVER_RV64M \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
|
||||
\
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
|
||||
\
|
||||
../src/cvw.sv \
|
||||
../testbench/testbench_imperas.sv \
|
||||
../testbench/common/*.sv \
|
||||
../src/*/*.sv \
|
||||
|
||||
@ -26,7 +26,8 @@ vlib work
|
||||
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
|
||||
vlog +incdir+../config/$1 \
|
||||
+incdir+../config/shared \
|
||||
../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \
|
||||
../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \
|
||||
../src/cvw.sv \
|
||||
../testbench/testbench_imperas.sv \
|
||||
../testbench/common/*.sv \
|
||||
../src/*/*.sv \
|
||||
|
||||
@ -30,13 +30,14 @@ vlog +incdir+../config/$1 \
|
||||
+define+USE_IMPERAS_DV \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
|
||||
../src/cvw.sv \
|
||||
../testbench/testbench_imperas.sv \
|
||||
../testbench/common/*.sv \
|
||||
../src/*/*.sv \
|
||||
|
||||
@ -33,9 +33,9 @@ vlib work
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
|
||||
vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
|
||||
#-- Run the Simulation
|
||||
@ -53,13 +53,14 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
+incdir+../config/shared \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
|
||||
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
|
||||
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
|
||||
../src/cvw.sv \
|
||||
../testbench/testbench-linux-imperas.sv \
|
||||
../testbench/common/*.sv ../src/*/*.sv \
|
||||
../src/*/*/*.sv -suppress 2583
|
||||
@ -93,7 +94,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
|
||||
} elseif {$2 eq "fpga"} {
|
||||
echo "hello"
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
|
||||
vsim workopt +nowarn3829 -fatal 7
|
||||
|
||||
@ -103,10 +104,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
|
||||
} else {
|
||||
if {$2 eq "ahb"} {
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
} else {
|
||||
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
}
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
|
||||
|
||||
|
||||
10
sim/wally.do
10
sim/wally.do
@ -33,7 +33,7 @@ vlib work
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
@ -47,7 +47,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "buildroot-no-trace"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
@ -68,7 +68,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
|
||||
} elseif {$2 eq "fpga"} {
|
||||
echo "hello"
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
|
||||
vsim workopt +nowarn3829 -fatal 7
|
||||
|
||||
@ -78,10 +78,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
|
||||
} else {
|
||||
if {$2 eq "ahb"} {
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
|
||||
} else {
|
||||
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
}
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
|
||||
|
||||
|
||||
6
sim/wally.xrun
Normal file
6
sim/wally.xrun
Normal file
@ -0,0 +1,6 @@
|
||||
xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv
|
||||
xrun -elaborate -top testbench ../testbench/testbench-xcelium.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench
|
||||
|
||||
|
||||
xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -top testbench -defparam testbench.TEST=arch64i
|
||||
|
||||
@ -7,8 +7,15 @@ add wave -noupdate /testbenchfp/Y
|
||||
add wave -noupdate /testbenchfp/Z
|
||||
add wave -noupdate /testbenchfp/Res
|
||||
add wave -noupdate /testbenchfp/Ans
|
||||
add wave -noupdate /testbenchfp/reset
|
||||
add wave -noupdate /testbenchfp/DivStart
|
||||
add wave -noupdate /testbenchfp/FDivBusyE
|
||||
add wave -noupdate /testbenchfp/CheckNow
|
||||
add wave -noupdate /testbenchfp/DivDone
|
||||
add wave -noupdate /testbenchfp/ResMatch
|
||||
add wave -noupdate /testbenchfp/FlagMatch
|
||||
add wave -noupdate /testbenchfp/CheckNow
|
||||
add wave -noupdate /testbenchfp/NaNGood
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
|
||||
|
||||
496
sim/wave.do
496
sim/wave.do
@ -6,47 +6,42 @@ add wave -noupdate /testbench/reset
|
||||
add wave -noupdate /testbench/reset_ext
|
||||
add wave -noupdate /testbench/memfilename
|
||||
add wave -noupdate /testbench/dut/core/SATP_REGW
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/PCD
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/PCE
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/PCF
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/PCM
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/PCM_temp
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/PCMOld
|
||||
add wave -noupdate /testbench/dut/core/InstrValidM
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
@ -79,29 +74,30 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
|
||||
add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||
add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
|
||||
add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
|
||||
add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
@ -120,8 +116,8 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/BALUControl
|
||||
add wave -noupdate -group alu -divider internals
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
|
||||
@ -152,28 +148,30 @@ add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/ebufsmarb/CurrState
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
|
||||
add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUReq
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
|
||||
add wave -noupdate -group AHB -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
|
||||
add wave -noupdate -group AHB /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
|
||||
@ -190,17 +188,17 @@ add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
@ -210,12 +208,12 @@ add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/d
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
@ -235,7 +233,7 @@ add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
@ -252,60 +250,59 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
@ -323,14 +320,7 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
@ -362,22 +352,27 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMASt
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
|
||||
@ -396,18 +391,6 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/un
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
|
||||
@ -462,16 +445,17 @@ add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
|
||||
add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||
add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
|
||||
add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
|
||||
add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
@ -483,54 +467,38 @@ add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
|
||||
@ -553,31 +521,31 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
|
||||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
|
||||
add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
|
||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
|
||||
add wave -noupdate -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
|
||||
add wave -noupdate -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
|
||||
add wave -noupdate -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
|
||||
add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
|
||||
@ -609,34 +577,38 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
|
||||
add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
|
||||
add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH
|
||||
add wave -noupdate /testbench/HPMCSample/EndSample
|
||||
add wave -noupdate /testbench/HPMCSample/StartSample
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/privmode/PrivilegeModeW
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/STATUS_MIE
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/clk
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrValidW
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/PCW
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrRawW
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/valid
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {23 ns} 0} {{Cursor 5} {394987 ns} 1}
|
||||
quietly wave cursor active 4
|
||||
WaveRestoreCursors {{Cursor 4} {6170 ns} 0} {{Cursor 4} {19809168 ns} 1}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
configure wave -justifyvalue left
|
||||
@ -651,4 +623,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {52 ns}
|
||||
WaveRestoreZoom {6124 ns} {6284 ns}
|
||||
|
||||
16
src/cache/cache.sv
vendored
16
src/cache/cache.sv
vendored
@ -27,9 +27,8 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
|
||||
module cache import cvw::*; #(parameter cvw_t P,
|
||||
parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
|
||||
@ -40,7 +39,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
input logic FlushCache, // Flush all dirty lines back to memory
|
||||
input logic InvalidateCache, // Clear all valid bits
|
||||
input logic [11:0] NextSet, // Virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] PAdr, // Physical address
|
||||
input logic [PA_BITS-1:0] PAdr, // Physical address
|
||||
input logic [(WORDLEN-1)/8:0] ByteMask, // Which bytes to write (D$ only)
|
||||
input logic [WORDLEN-1:0] CacheWriteData, // Data to write to cache (D$ only)
|
||||
output logic CacheCommitted, // Cache has started bus operation that shouldn't be interrupted
|
||||
@ -57,7 +56,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
input logic [LOGBWPL-1:0] BeatCount, // Beat in burst
|
||||
input logic [LINELEN-1:0] FetchBuffer, // Buffer long enough to hold entire cache line arriving from bus
|
||||
output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
|
||||
output logic [`PA_BITS-1:0] CacheBusAdr // Address for bus access
|
||||
output logic [PA_BITS-1:0] CacheBusAdr // Address for bus access
|
||||
);
|
||||
|
||||
// Cache parameters
|
||||
@ -65,7 +64,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
localparam OFFSETLEN = $clog2(LINEBYTELEN); // Number of bits in offset field
|
||||
localparam SETLEN = $clog2(NUMLINES); // Number of set bits
|
||||
localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits
|
||||
localparam TAGLEN = `PA_BITS - SETTOP; // Number of tag bits
|
||||
localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits
|
||||
localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
|
||||
localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
|
||||
localparam FLUSHADRTHRESHOLD = NUMLINES - 1; // Used to determine when flush is complete
|
||||
@ -114,7 +113,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
AdrSelMuxSel, CacheSet);
|
||||
|
||||
// Array of cache ways, along with victim, hit, dirty, and read merging logic
|
||||
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
|
||||
cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
|
||||
.clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
|
||||
.SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
|
||||
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
|
||||
@ -152,7 +151,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
.PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
|
||||
|
||||
// Bus address for fetch, writeback, or flush writeback
|
||||
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
|
||||
mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
|
||||
.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
|
||||
.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
|
||||
.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
|
||||
@ -184,6 +183,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
|
||||
assign LineWriteData = FetchBuffer;
|
||||
assign LineByteMask = '1;
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Flush logic
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
7
src/cache/cacheLRU.sv
vendored
7
src/cache/cacheLRU.sv
vendored
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cacheLRU
|
||||
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
|
||||
input logic clk,
|
||||
@ -104,8 +102,7 @@ module cacheLRU
|
||||
if (node == NUMWAYS-2) begin
|
||||
assign LRUUpdate[lchild] = ~WayEncoded[r];
|
||||
assign LRUUpdate[rchild] = WayEncoded[r];
|
||||
end
|
||||
else begin
|
||||
end else begin
|
||||
assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
|
||||
assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
|
||||
end
|
||||
@ -113,7 +110,7 @@ module cacheLRU
|
||||
|
||||
// The root node of the LRU tree will always be selected in LRUUpdate. No mux needed.
|
||||
assign NextLRU[NUMWAYS-2] = ~WayExpanded[NUMWAYS-2];
|
||||
mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
|
||||
if (NUMWAYS > 2) mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
|
||||
|
||||
// Compute next victim way.
|
||||
for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin
|
||||
|
||||
7
src/cache/cachefsm.sv
vendored
7
src/cache/cachefsm.sv
vendored
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cachefsm #(parameter READ_ONLY_CACHE = 0) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
@ -94,7 +92,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
|
||||
assign FlushFlag = FlushAdrFlag & FlushWayFlag;
|
||||
|
||||
// outputs for the performance counters.
|
||||
assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
|
||||
assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) |
|
||||
(CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
|
||||
assign CacheMiss = CacheAccess & ~CacheHit;
|
||||
|
||||
// special case on reset. When the fsm first exists reset the
|
||||
@ -159,7 +158,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
|
||||
assign SelFlush = (CurrState == STATE_READY & FlushCache) |
|
||||
(CurrState == STATE_FLUSH) |
|
||||
(CurrState == STATE_FLUSH_WRITEBACK);
|
||||
// coverage off -item e -fecexprrow 1
|
||||
// coverage off -item e 1 -fecexprrow 1
|
||||
// (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck)
|
||||
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
|
||||
(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
|
||||
|
||||
43
src/cache/cacheway.sv
vendored
43
src/cache/cacheway.sv
vendored
@ -27,16 +27,15 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
module cacheway import cvw::*; #(parameter cvw_t P,
|
||||
parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
|
||||
input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
|
||||
input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
|
||||
input logic [`PA_BITS-1:0] PAdr, // Physical address
|
||||
input logic [PA_BITS-1:0] PAdr, // Physical address
|
||||
input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only)
|
||||
input logic SetValid, // Set the valid bit in the selected way and set
|
||||
input logic SetDirty, // Set the dirty bit in the selected way and set
|
||||
@ -54,11 +53,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
output logic DirtyWay, // This way is dirty
|
||||
output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
|
||||
|
||||
localparam WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam WORDSPERLINE = LINELEN/XLEN;
|
||||
localparam BYTESPERLINE = LINELEN/8;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
localparam BYTESPERWORD = `XLEN/8;
|
||||
localparam LOGXLENBYTES = $clog2(XLEN/8);
|
||||
localparam BYTESPERWORD = XLEN/8;
|
||||
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
@ -82,10 +81,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
|
||||
|
||||
// FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
|
||||
// coverage off -item e 1 -fecexprrow 3
|
||||
// nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
|
||||
assign FlushWayEn = FlushWay & SelFlush;
|
||||
assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
|
||||
end
|
||||
else begin:flushlogic // no flush operation for read-only caches.
|
||||
end else begin:flushlogic // no flush operation for read-only caches.
|
||||
assign SelTag = VictimWay;
|
||||
assign SelNonHit = SetValid;
|
||||
end
|
||||
@ -100,7 +100,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay
|
||||
assign ClearDirtyWay = ClearDirty & SelData;
|
||||
assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
|
||||
assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN
|
||||
assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN
|
||||
|
||||
// If writing the whole line set all write enables to 1, else only set the correct word.
|
||||
assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
|
||||
@ -109,14 +109,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
// Tag Array
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
|
||||
ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
|
||||
.addr(CacheSet), .dout(ReadTag),
|
||||
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
|
||||
.din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
|
||||
|
||||
// AND portion of distributed tag multiplexer
|
||||
assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
|
||||
assign DirtyWay = SelTag & Dirty & ValidWay;
|
||||
assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
|
||||
assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Data Array
|
||||
@ -124,20 +124,19 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
|
||||
genvar words;
|
||||
|
||||
localparam SRAMLEN = 128;
|
||||
localparam SRAMLEN = 128; // *** make this a global parameter
|
||||
localparam NUMSRAM = LINELEN/SRAMLEN;
|
||||
localparam SRAMLENINBYTES = SRAMLEN/8;
|
||||
localparam LOGNUMSRAM = $clog2(NUMSRAM);
|
||||
|
||||
for(words = 0; words < NUMSRAM; words++) begin: word
|
||||
if (!READ_ONLY_CACHE) begin:wordram
|
||||
ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
|
||||
ram1p1rwbe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
|
||||
.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
|
||||
end
|
||||
else begin:wordram // no byte-enable needed for i$.
|
||||
ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
|
||||
end else begin:wordram // no byte-enable needed for i$.
|
||||
ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
|
||||
.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
|
||||
.we(SelectedWriteWordEn));
|
||||
@ -154,8 +153,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
always_ff @(posedge clk) begin // Valid bit array,
|
||||
if (reset) ValidBits <= #1 '0;
|
||||
if(CacheEn) begin
|
||||
ValidWay <= #1 ValidBits[CacheSet];
|
||||
if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
|
||||
ValidWay <= #1 ValidBits[CacheSet];
|
||||
if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
|
||||
else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay;
|
||||
end
|
||||
end
|
||||
@ -175,8 +174,4 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
end
|
||||
end
|
||||
end else assign Dirty = 1'b0;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
7
src/cache/subcachelineread.sv
vendored
7
src/cache/subcachelineread.sv
vendored
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module subcachelineread #(parameter LINELEN, WORDLEN,
|
||||
parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
|
||||
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
|
||||
@ -43,9 +41,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
|
||||
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
|
||||
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
|
||||
|
||||
if (PADLEN > 0) begin
|
||||
assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
|
||||
end else assign ReadDataLinePad = ReadDataLine;
|
||||
if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
|
||||
else assign ReadDataLinePad = ReadDataLine;
|
||||
|
||||
genvar index;
|
||||
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
|
||||
|
||||
272
src/cvw.sv
Normal file
272
src/cvw.sv
Normal file
@ -0,0 +1,272 @@
|
||||
//////////////////////////////////////////
|
||||
// cvw.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 27 January 2022
|
||||
//
|
||||
// Purpose: package with shared CORE-V-Wally global parameters
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Usiing global `define statements isn't ideal in a large SystemVerilog system because
|
||||
// of the risk of `define name conflicts across different subsystems.
|
||||
// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
|
||||
// that is referenced by all Wally modules but not by other subsystems.
|
||||
|
||||
`ifndef CVW_T
|
||||
|
||||
`define CVW_T 1
|
||||
|
||||
package cvw;
|
||||
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
typedef struct packed {
|
||||
logic FPGA; // Modifications to tare
|
||||
logic QEMU; // Hacks to agree with QEMU during Linux boot
|
||||
int XLEN; // Machine width (32 or 64)
|
||||
logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
|
||||
int MISA; // Machine Instruction Set Architecture
|
||||
int AHBW; // AHB bus width (usually = XLEN)
|
||||
|
||||
// RISC-V Features
|
||||
logic ZICSR_SUPPORTED;
|
||||
logic ZIFENCEI_SUPPORTED;
|
||||
logic [11:0] COUNTERS;
|
||||
logic ZICNTR_SUPPORTED;
|
||||
logic ZIHPM_SUPPORTED;
|
||||
logic ZFH_SUPPORTED;
|
||||
logic SSTC_SUPPORTED;
|
||||
logic VIRTMEM_SUPPORTED;
|
||||
logic VECTORED_INTERRUPTS_SUPPORTED;
|
||||
logic BIGENDIAN_SUPPORTED;
|
||||
logic SVADU_SUPPORTED;
|
||||
logic ZMMUL_SUPPORTED;
|
||||
logic ZICBOM_SUPPORTED;
|
||||
logic ZICBOZ_SUPPORTED;
|
||||
logic ZICBOP_SUPPORTED;
|
||||
logic SVPBMT_SUPPORTED;
|
||||
logic SVINVAL_SUPPORTED;
|
||||
|
||||
// Microarchitectural Features
|
||||
logic BUS_SUPPORTED;
|
||||
logic DCACHE_SUPPORTED;
|
||||
logic ICACHE_SUPPORTED;
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
int ITLB_ENTRIES;
|
||||
int DTLB_ENTRIES;
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 ints per way, 256 bit or more lines
|
||||
int DCACHE_NUMWAYS;
|
||||
int DCACHE_WAYSIZEINBYTES;
|
||||
int DCACHE_LINELENINBITS;
|
||||
int ICACHE_NUMWAYS;
|
||||
int ICACHE_WAYSIZEINBYTES;
|
||||
int ICACHE_LINELENINBITS;
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
int IDIV_BITSPERCYCLE;
|
||||
logic IDIV_ON_FPU;
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
int PMP_ENTRIES;
|
||||
|
||||
// Address space
|
||||
logic [63:0] RESET_VECTOR;
|
||||
|
||||
// WFI Timeout Wait
|
||||
int WFI_TIMEOUT_BIT;
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
logic DTIM_SUPPORTED;
|
||||
logic [63:0] DTIM_BASE;
|
||||
logic [63:0] DTIM_RANGE;
|
||||
logic IROM_SUPPORTED;
|
||||
logic [63:0] IROM_BASE;
|
||||
logic [63:0] IROM_RANGE;
|
||||
logic BOOTROM_SUPPORTED;
|
||||
logic [63:0] BOOTROM_BASE;
|
||||
logic [63:0] BOOTROM_RANGE;
|
||||
logic UNCORE_RAM_SUPPORTED;
|
||||
logic [63:0] UNCORE_RAM_BASE;
|
||||
logic [63:0] UNCORE_RAM_RANGE;
|
||||
logic EXT_MEM_SUPPORTED;
|
||||
logic [63:0] EXT_MEM_BASE;
|
||||
logic [63:0] EXT_MEM_RANGE;
|
||||
logic CLINT_SUPPORTED;
|
||||
logic [63:0] CLINT_BASE;
|
||||
logic [63:0] CLINT_RANGE;
|
||||
logic GPIO_SUPPORTED;
|
||||
logic [63:0] GPIO_BASE;
|
||||
logic [63:0] GPIO_RANGE;
|
||||
logic UART_SUPPORTED;
|
||||
logic [63:0] UART_BASE;
|
||||
logic [63:0] UART_RANGE;
|
||||
logic PLIC_SUPPORTED;
|
||||
logic [63:0] PLIC_BASE;
|
||||
logic [63:0] PLIC_RANGE;
|
||||
logic SDC_SUPPORTED;
|
||||
logic [63:0] SDC_BASE;
|
||||
logic [63:0] SDC_RANGE;
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
logic GPIO_LOOPBACK_TEST;
|
||||
|
||||
// Hardware configuration
|
||||
int UART_PRESCALE ;
|
||||
|
||||
// Interrupt configuration
|
||||
int PLIC_NUM_SRC;
|
||||
logic PLIC_NUM_SRC_LT_32;
|
||||
int PLIC_GPIO_ID;
|
||||
int PLIC_UART_ID;
|
||||
|
||||
logic BPRED_SUPPORTED;
|
||||
BranchPredictorType BPRED_TYPE;
|
||||
int BPRED_NUM_LHR;
|
||||
int BPRED_SIZE;
|
||||
int BTB_SIZE;
|
||||
|
||||
// FPU division architecture
|
||||
int RADIX;
|
||||
int DIVCOPIES;
|
||||
|
||||
// bit manipulation
|
||||
logic ZBA_SUPPORTED;
|
||||
logic ZBB_SUPPORTED;
|
||||
logic ZBC_SUPPORTED;
|
||||
logic ZBS_SUPPORTED;
|
||||
|
||||
// Memory synthesis configuration
|
||||
logic USE_SRAM;
|
||||
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
logic [1:0] M_MODE ;
|
||||
logic [1:0] S_MODE ;
|
||||
logic [1:0] U_MODE ;
|
||||
|
||||
// Virtual Memory Constants
|
||||
int VPN_SEGMENT_BITS;
|
||||
int VPN_BITS;
|
||||
int PPN_BITS;
|
||||
int PA_BITS;
|
||||
int SVMODE_BITS;
|
||||
int ASID_BASE;
|
||||
int ASID_BITS;
|
||||
|
||||
// constants to check SATP_MODE against
|
||||
// defined in Table 4.3 of the privileged spec
|
||||
logic [3:0] NO_TRANSLATE;
|
||||
logic [3:0] SV32;
|
||||
logic [3:0] SV39;
|
||||
logic [3:0] SV48;
|
||||
|
||||
// macros to define supported modes
|
||||
logic A_SUPPORTED;
|
||||
logic B_SUPPORTED;
|
||||
logic C_SUPPORTED;
|
||||
logic D_SUPPORTED;
|
||||
logic E_SUPPORTED;
|
||||
logic F_SUPPORTED;
|
||||
logic I_SUPPORTED;
|
||||
logic M_SUPPORTED;
|
||||
logic Q_SUPPORTED;
|
||||
logic S_SUPPORTED;
|
||||
logic U_SUPPORTED;
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
int LOG_XLEN;
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
int PMPCFG_ENTRIES;
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
int Q_LEN;
|
||||
int Q_NE;
|
||||
int Q_NF;
|
||||
int Q_BIAS;
|
||||
logic [1:0] Q_FMT;
|
||||
int D_LEN;
|
||||
int D_NE;
|
||||
int D_NF;
|
||||
int D_BIAS;
|
||||
logic [1:0] D_FMT;
|
||||
int S_LEN;
|
||||
int S_NE;
|
||||
int S_NF;
|
||||
int S_BIAS;
|
||||
logic [1:0] S_FMT;
|
||||
int H_LEN;
|
||||
int H_NE;
|
||||
int H_NF;
|
||||
int H_BIAS;
|
||||
logic [1:0] H_FMT;
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
int FLEN;
|
||||
int NE ;
|
||||
int NF ;
|
||||
logic [1:0] FMT ;
|
||||
int BIAS;
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
int FPSIZES;
|
||||
int FMTBITS;
|
||||
int LEN1 ;
|
||||
int NE1 ;
|
||||
int NF1 ;
|
||||
logic [1:0] FMT1 ;
|
||||
int BIAS1;
|
||||
int LEN2 ;
|
||||
int NE2 ;
|
||||
int NF2 ;
|
||||
logic [1:0] FMT2 ;
|
||||
int BIAS2;
|
||||
|
||||
// largest length in IEU/FPU
|
||||
int CVTLEN;
|
||||
int LLEN;
|
||||
int LOGCVTLEN;
|
||||
int NORMSHIFTSZ;
|
||||
int LOGNORMSHIFTSZ;
|
||||
int CORRSHIFTSZ;
|
||||
|
||||
// division constants
|
||||
int DIVN ;
|
||||
int LOGR ;
|
||||
int RK ;
|
||||
int LOGRK ;
|
||||
int FPDUR ;
|
||||
int DURLEN ;
|
||||
int DIVb ;
|
||||
int DIVBLEN ;
|
||||
int DIVa ;
|
||||
|
||||
} cvw_t;
|
||||
|
||||
endpackage
|
||||
|
||||
`endif
|
||||
@ -27,9 +27,10 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ahbcacheinterface #(
|
||||
parameter AHBW,
|
||||
parameter LLEN,
|
||||
parameter PA_BITS,
|
||||
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
|
||||
parameter AHBWLOGBWPL, // Log2 of ^
|
||||
parameter LINELEN, // Number of bits in cacheline
|
||||
@ -44,14 +45,14 @@ module ahbcacheinterface #(
|
||||
output logic [2:0] HSIZE, // AHB transaction width
|
||||
output logic [2:0] HBURST, // AHB burst length
|
||||
// bus interface buses
|
||||
input logic [`AHBW-1:0] HRDATA, // AHB read data
|
||||
output logic [`PA_BITS-1:0] HADDR, // AHB address
|
||||
output logic [`AHBW-1:0] HWDATA, // AHB write data
|
||||
output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask
|
||||
input logic [AHBW-1:0] HRDATA, // AHB read data
|
||||
output logic [PA_BITS-1:0] HADDR, // AHB address
|
||||
output logic [AHBW-1:0] HWDATA, // AHB write data
|
||||
output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask
|
||||
|
||||
// cache interface
|
||||
input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
|
||||
input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
|
||||
input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line
|
||||
input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
|
||||
input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
|
||||
input logic Cacheable, // Memory operation is cachable
|
||||
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
|
||||
@ -61,8 +62,8 @@ module ahbcacheinterface #(
|
||||
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
|
||||
|
||||
// uncached interface
|
||||
input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
|
||||
input logic [`LLEN-1:0] WriteDataM, // IEU write data for uncached store
|
||||
input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation
|
||||
input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store
|
||||
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
|
||||
input logic [2:0] Funct3, // Size of uncached memory operation
|
||||
|
||||
@ -74,11 +75,11 @@ module ahbcacheinterface #(
|
||||
|
||||
|
||||
localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
|
||||
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
|
||||
logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
|
||||
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
|
||||
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
|
||||
logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
|
||||
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
|
||||
logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
|
||||
logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data
|
||||
|
||||
genvar index;
|
||||
|
||||
@ -86,35 +87,35 @@ module ahbcacheinterface #(
|
||||
for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
|
||||
logic [BEATSPERLINE-1:0] CaptureBeat;
|
||||
assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
|
||||
flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
|
||||
.q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW]));
|
||||
flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
|
||||
.q(FetchBuffer[(index+1)*AHBW-1:index*AHBW]));
|
||||
end
|
||||
|
||||
mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
|
||||
assign HADDR = ({{`PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR;
|
||||
mux2 #(PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
|
||||
assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR;
|
||||
|
||||
mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
|
||||
mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
|
||||
|
||||
// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
|
||||
logic [`AHBW-1:0] CacheReadDataWordAHB;
|
||||
logic [AHBW-1:0] CacheReadDataWordAHB;
|
||||
if(LLENPOVERAHBW > 1) begin
|
||||
logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
|
||||
logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
|
||||
genvar index;
|
||||
for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
|
||||
assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
|
||||
assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)];
|
||||
end
|
||||
assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
|
||||
end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
|
||||
end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0];
|
||||
|
||||
mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
|
||||
mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]),
|
||||
.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
|
||||
flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
|
||||
flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
|
||||
|
||||
// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
|
||||
// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
|
||||
swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
|
||||
swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
|
||||
|
||||
flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
|
||||
flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB);
|
||||
|
||||
buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
|
||||
.HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
|
||||
|
||||
@ -27,9 +27,8 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ahbinterface #(
|
||||
parameter XLEN,
|
||||
parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
|
||||
)(
|
||||
input logic HCLK, HRESETn,
|
||||
@ -37,30 +36,30 @@ module ahbinterface #(
|
||||
input logic HREADY, // AHB peripheral ready
|
||||
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
|
||||
output logic HWRITE, // AHB 0: Read operation 1: Write operation
|
||||
input logic [`XLEN-1:0] HRDATA, // AHB read data
|
||||
output logic [`XLEN-1:0] HWDATA, // AHB write data
|
||||
output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask
|
||||
input logic [XLEN-1:0] HRDATA, // AHB read data
|
||||
output logic [XLEN-1:0] HWDATA, // AHB write data
|
||||
output logic [XLEN/8-1:0] HWSTRB, // AHB byte mask
|
||||
|
||||
// lsu/ifu interface
|
||||
input logic Stall, // Core pipeline is stalled
|
||||
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
|
||||
input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
|
||||
input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word
|
||||
input logic [`XLEN-1:0] WriteData, // IEU write data for a store
|
||||
input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word
|
||||
input logic [XLEN-1:0] WriteData, // IEU write data for a store
|
||||
output logic BusStall, // Bus is busy with an in flight memory operation
|
||||
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
|
||||
output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus
|
||||
output logic [(LSU ? XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus
|
||||
);
|
||||
|
||||
logic CaptureEn;
|
||||
localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU
|
||||
localparam LEN = (LSU ? XLEN : 32); // 32 bits for IFU, XLEN for LSU
|
||||
|
||||
flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
|
||||
|
||||
if(LSU) begin
|
||||
// delay HWDATA by 1 cycle per spec; assumes AHBW = XLEN
|
||||
flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA);
|
||||
flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
|
||||
flop #(XLEN) wdreg(HCLK, WriteData, HWDATA);
|
||||
flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
|
||||
end else begin
|
||||
assign HWDATA = '0;
|
||||
assign HWSTRB = '0;
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance.
|
||||
|
||||
// HCLK and clk must be the same clock!
|
||||
|
||||
@ -27,8 +27,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// HCLK and clk must be the same clock!
|
||||
module busfsm (
|
||||
input logic HCLK,
|
||||
|
||||
@ -31,9 +31,8 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module controllerinput #(
|
||||
parameter PA_BITS,
|
||||
parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs
|
||||
)(
|
||||
input logic HCLK,
|
||||
@ -47,14 +46,14 @@ module controllerinput #(
|
||||
input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
|
||||
input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
|
||||
input logic [2:0] HBURSTIn, // Manager input. AHB burst length
|
||||
input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address
|
||||
input logic [PA_BITS-1:0] HADDRIn, // Manager input. AHB address
|
||||
output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
|
||||
// controller output
|
||||
output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
|
||||
output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation
|
||||
output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width
|
||||
output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length
|
||||
output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
|
||||
output logic [PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
|
||||
input logic HREADYIn // Peripheral ready
|
||||
);
|
||||
|
||||
@ -62,13 +61,13 @@ module controllerinput #(
|
||||
logic [2:0] HSIZESave;
|
||||
logic [2:0] HBURSTSave;
|
||||
logic [1:0] HTRANSSave;
|
||||
logic [`PA_BITS-1:0] HADDRSave;
|
||||
logic [PA_BITS-1:0] HADDRSave;
|
||||
|
||||
if (SAVE_ENABLED) begin
|
||||
flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
|
||||
flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
|
||||
{HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
|
||||
{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
|
||||
mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
|
||||
mux2 #(1+3+3+2+PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn},
|
||||
{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
|
||||
Restore,
|
||||
{HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
|
||||
@ -84,6 +83,3 @@ module controllerinput #(
|
||||
assign HREADYOut = HREADYIn & ~Disable;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
@ -31,33 +31,31 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ebu (
|
||||
module ebu #(parameter XLEN, PA_BITS, AHBW)(
|
||||
input logic clk, reset,
|
||||
// Signals from IFU
|
||||
input logic [1:0] IFUHTRANS, // IFU AHB transaction request
|
||||
input logic [2:0] IFUHSIZE, // IFU AHB transaction size
|
||||
input logic [2:0] IFUHBURST, // IFU AHB burst length
|
||||
input logic [`PA_BITS-1:0] IFUHADDR, // IFU AHB address
|
||||
input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address
|
||||
output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant
|
||||
// Signals from LSU
|
||||
input logic [1:0] LSUHTRANS, // LSU AHB transaction request
|
||||
input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
|
||||
input logic [2:0] LSUHSIZE, // LSU AHB size
|
||||
input logic [2:0] LSUHBURST, // LSU AHB burst length
|
||||
input logic [`PA_BITS-1:0] LSUHADDR, // LSU AHB address
|
||||
input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
|
||||
input logic [`XLEN/8-1:0] LSUHWSTRB, // AHB byte mask
|
||||
input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address
|
||||
input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
|
||||
input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask
|
||||
output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
|
||||
|
||||
// AHB-Lite external signals
|
||||
output logic HCLK, HRESETn,
|
||||
input logic HREADY, // AHB peripheral ready
|
||||
input logic HRESP, // AHB peripheral response. 0: OK 1: Error
|
||||
output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
|
||||
output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration
|
||||
output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
|
||||
output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
|
||||
output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration
|
||||
output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
|
||||
output logic HWRITE, // AHB transaction direction after arbitration
|
||||
output logic [2:0] HSIZE, // AHB transaction size after arbitration
|
||||
output logic [2:0] HBURST, // AHB burst length after arbitration
|
||||
@ -73,13 +71,13 @@ module ebu (
|
||||
logic IFUDisable;
|
||||
logic IFUSelect;
|
||||
|
||||
logic [`PA_BITS-1:0] IFUHADDROut;
|
||||
logic [PA_BITS-1:0] IFUHADDROut;
|
||||
logic [1:0] IFUHTRANSOut;
|
||||
logic [2:0] IFUHBURSTOut;
|
||||
logic [2:0] IFUHSIZEOut;
|
||||
logic IFUHWRITEOut;
|
||||
|
||||
logic [`PA_BITS-1:0] LSUHADDROut;
|
||||
logic [PA_BITS-1:0] LSUHADDROut;
|
||||
logic [1:0] LSUHTRANSOut;
|
||||
logic [2:0] LSUHBURSTOut;
|
||||
logic [2:0] LSUHSIZEOut;
|
||||
@ -98,14 +96,14 @@ module ebu (
|
||||
// input stages and muxing for IFU and LSU
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
controllerinput IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
|
||||
controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
|
||||
.Request(IFUReq),
|
||||
.HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
|
||||
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
|
||||
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
|
||||
|
||||
// LSU always has priority so there should never be a need to save and restore the address phase inputs.
|
||||
controllerinput #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
|
||||
controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
|
||||
.Request(LSUReq),
|
||||
.HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
|
||||
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
|
||||
|
||||
@ -28,8 +28,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ebufsmarb (
|
||||
input logic HCLK,
|
||||
input logic HRESETn,
|
||||
|
||||
@ -25,16 +25,15 @@
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fclassify (
|
||||
module fclassify import cvw::*; #(parameter cvw_t P) (
|
||||
input logic Xs, // sign bit
|
||||
input logic XNaN, // is NaN
|
||||
input logic XSNaN, // is signaling NaN
|
||||
input logic XSubnorm, // is Subnormal
|
||||
input logic XZero, // is zero
|
||||
input logic XInf, // is infinity
|
||||
output logic [`XLEN-1:0] ClassRes // classify result
|
||||
output logic [P.XLEN-1:0] ClassRes // classify result
|
||||
);
|
||||
|
||||
logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal
|
||||
@ -63,6 +62,6 @@ module fclassify (
|
||||
// bit 7 - +Inf
|
||||
// bit 8 - signaling NaN
|
||||
// bit 9 - quiet NaN
|
||||
assign ClassRes = {{`XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
|
||||
assign ClassRes = {{P.XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
|
||||
///////////////////////////////////////////
|
||||
// fcmp.sv
|
||||
//
|
||||
@ -27,8 +26,6 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// OpCtrl values
|
||||
// 110 min
|
||||
// 101 max
|
||||
@ -36,25 +33,25 @@
|
||||
// 001 less than
|
||||
// 011 less than or equal
|
||||
|
||||
module fcmp (
|
||||
input logic [`FMTBITS-1:0] Fmt, // format of fp number
|
||||
input logic [2:0] OpCtrl, // see above table
|
||||
input logic Xs, Ys, // input signs
|
||||
input logic [`NE-1:0] Xe, Ye, // input exponents
|
||||
input logic [`NF:0] Xm, Ym, // input mantissa
|
||||
input logic XZero, YZero, // is zero
|
||||
input logic XNaN, YNaN, // is NaN
|
||||
input logic XSNaN, YSNaN, // is signaling NaN
|
||||
input logic [`FLEN-1:0] X, Y, // original inputs (before unpacker)
|
||||
output logic CmpNV, // invalid flag
|
||||
output logic [`FLEN-1:0] CmpFpRes, // compare floating-point result
|
||||
output logic [`XLEN-1:0] CmpIntRes // compare integer result
|
||||
module fcmp import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.FMTBITS-1:0] Fmt, // format of fp number
|
||||
input logic [2:0] OpCtrl, // see above table
|
||||
input logic Xs, Ys, // input signs
|
||||
input logic [P.NE-1:0] Xe, Ye, // input exponents
|
||||
input logic [P.NF:0] Xm, Ym, // input mantissa
|
||||
input logic XZero, YZero, // is zero
|
||||
input logic XNaN, YNaN, // is NaN
|
||||
input logic XSNaN, YSNaN, // is signaling NaN
|
||||
input logic [P.FLEN-1:0] X, Y, // original inputs (before unpacker)
|
||||
output logic CmpNV, // invalid flag
|
||||
output logic [P.FLEN-1:0] CmpFpRes, // compare floating-point result
|
||||
output logic [P.XLEN-1:0] CmpIntRes // compare integer result
|
||||
);
|
||||
|
||||
logic LTabs, LT, EQ; // is X < or > or = Y
|
||||
logic [`FLEN-1:0] NaNRes; // NaN result
|
||||
logic BothZero; // are both inputs zero
|
||||
logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
|
||||
logic LTabs, LT, EQ; // is X < or > or = Y
|
||||
logic [P.FLEN-1:0] NaNRes; // NaN result
|
||||
logic BothZero; // are both inputs zero
|
||||
logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
|
||||
|
||||
assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
|
||||
assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
|
||||
@ -64,7 +61,6 @@ module fcmp (
|
||||
assign EitherNaN = XNaN|YNaN;
|
||||
assign EitherSNaN = XSNaN|YSNaN;
|
||||
|
||||
|
||||
// flags
|
||||
// Min/Max - if an input is a signaling NaN set invalid flag
|
||||
// LT/LE - signaling - sets invalid if NaN input
|
||||
@ -85,47 +81,46 @@ module fcmp (
|
||||
// for RISC-V, return the canonical NaN
|
||||
|
||||
// select the NaN result
|
||||
if (`FPSIZES == 1)
|
||||
if(`IEEE754) assign NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
|
||||
else assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
if (P.FPSIZES == 1)
|
||||
if(P.IEEE754) assign NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
|
||||
else assign NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
|
||||
|
||||
else if (`FPSIZES == 2)
|
||||
if(`IEEE754) assign NaNRes = Fmt ? {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
|
||||
else assign NaNRes = Fmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
else if (P.FPSIZES == 2)
|
||||
if(P.IEEE754) assign NaNRes = Fmt ? {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
|
||||
else assign NaNRes = Fmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
|
||||
|
||||
else if (`FPSIZES == 3)
|
||||
else if (P.FPSIZES == 3)
|
||||
always_comb
|
||||
case (Fmt)
|
||||
`FMT:
|
||||
if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
|
||||
else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
`FMT1:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
|
||||
else NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
|
||||
`FMT2:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, Xs, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
|
||||
else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
|
||||
default: NaNRes = {`FLEN{1'bx}};
|
||||
P.FMT:
|
||||
if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
|
||||
else NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
|
||||
P.FMT1:
|
||||
if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
|
||||
else NaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
|
||||
P.FMT2:
|
||||
if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN2{1'b1}}, Xs, {P.NE2{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF2]};
|
||||
else NaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
|
||||
default: NaNRes = {P.FLEN{1'bx}};
|
||||
endcase
|
||||
|
||||
else if (`FPSIZES == 4)
|
||||
else if (P.FPSIZES == 4)
|
||||
always_comb
|
||||
case (Fmt)
|
||||
2'h3:
|
||||
if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
|
||||
else NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
|
||||
if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
|
||||
else NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
|
||||
2'h1:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, Xs, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
|
||||
else NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
|
||||
if(P.IEEE754) NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, Xs, {P.D_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.D_NF]};
|
||||
else NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
|
||||
2'h0:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, Xs, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
|
||||
else NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
|
||||
if(P.IEEE754) NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, Xs, {P.S_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.S_NF]};
|
||||
else NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
|
||||
2'h2:
|
||||
if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, Xs, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
|
||||
else NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
|
||||
if(P.IEEE754) NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, Xs, {P.H_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.H_NF]};
|
||||
else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
|
||||
endcase
|
||||
|
||||
|
||||
// Min/Max
|
||||
// - outputs the min/max of X and Y
|
||||
// - -0 < 0
|
||||
@ -155,6 +150,5 @@ module fcmp (
|
||||
// - -0 = 0
|
||||
// - inf = inf and -inf = -inf
|
||||
// - return 0 if comparison with NaN (unordered)
|
||||
assign CmpIntRes = {(`XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
|
||||
|
||||
assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
|
||||
endmodule
|
||||
|
||||
144
src/fpu/fctrl.sv
144
src/fpu/fctrl.sv
@ -25,69 +25,69 @@
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fctrl (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
module fctrl import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
// input control signals
|
||||
input logic StallE, StallM, StallW, // stall signals
|
||||
input logic FlushE, FlushM, FlushW, // flush signals
|
||||
input logic IntDivE, // is inteteger division
|
||||
input logic [2:0] FRM_REGW, // rounding mode from CSR
|
||||
input logic [1:0] STATUS_FS, // is FPU enabled?
|
||||
input logic FDivBusyE, // is the divider busy
|
||||
// intruction
|
||||
input logic [31:0] InstrD, // the full instruction
|
||||
input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
|
||||
input logic [6:0] OpD, // bits 6:0 of instruction
|
||||
input logic [4:0] Rs2D, // bits 24:20 of instruction
|
||||
input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
|
||||
input logic StallE, StallM, StallW, // stall signals
|
||||
input logic FlushE, FlushM, FlushW, // flush signals
|
||||
input logic IntDivE, // is inteteger division
|
||||
input logic [2:0] FRM_REGW, // rounding mode from CSR
|
||||
input logic [1:0] STATUS_FS, // is FPU enabled?
|
||||
input logic FDivBusyE, // is the divider busy
|
||||
// instruction
|
||||
input logic [31:0] InstrD, // the full instruction
|
||||
input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
|
||||
input logic [6:0] OpD, // bits 6:0 of instruction
|
||||
input logic [4:0] Rs2D, // bits 24:20 of instruction
|
||||
input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode
|
||||
// input mux selections
|
||||
output logic XEnD, YEnD, ZEnD, // enable inputs
|
||||
output logic XEnE, YEnE, ZEnE, // enable inputs
|
||||
output logic XEnD, YEnD, ZEnD, // enable inputs
|
||||
output logic XEnE, YEnE, ZEnE, // enable inputs
|
||||
// opperation mux selections
|
||||
output logic FCvtIntE, FCvtIntW, // convert to integer opperation
|
||||
output logic [2:0] FrmM, // FP rounding mode
|
||||
output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format
|
||||
output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
|
||||
output logic FpLoadStoreM, // FP load or store instruction
|
||||
output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit
|
||||
output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
|
||||
output logic FCvtIntE, FCvtIntW, // convert to integer opperation
|
||||
output logic [2:0] FrmM, // FP rounding mode
|
||||
output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format
|
||||
output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
|
||||
output logic FpLoadStoreM, // FP load or store instruction
|
||||
output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit
|
||||
output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
|
||||
output logic FPUActiveE, // FP instruction being executed
|
||||
// register control signals
|
||||
output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
|
||||
output logic FWriteIntE, FWriteIntM, // Write to integer register
|
||||
output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input
|
||||
output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input
|
||||
output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
|
||||
output logic FWriteIntE, FWriteIntM, // Write to integer register
|
||||
output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input
|
||||
output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input
|
||||
// other control signals
|
||||
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||
output logic FDivStartE, IDivStartE // Start division or squareroot
|
||||
output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
||||
output logic FDivStartE, IDivStartE // Start division or squareroot
|
||||
);
|
||||
|
||||
`define FCTRLW 12
|
||||
|
||||
logic [`FCTRLW-1:0] ControlsD; // control signals
|
||||
logic FRegWriteD; // FP register write enable
|
||||
logic FDivStartD; // start division/sqrt
|
||||
logic FWriteIntD; // integer register write enable
|
||||
logic [2:0] OpCtrlD; // Select which opperation to do in each component
|
||||
logic [1:0] PostProcSelD; // select result in the post processing unit
|
||||
logic [1:0] FResSelD; // Select one of the results that finish in the memory stage
|
||||
logic [2:0] FrmD, FrmE; // FP rounding mode
|
||||
logic [`FMTBITS-1:0] FmtD; // FP format
|
||||
logic [1:0] Fmt, Fmt2; // format - before possible reduction
|
||||
logic SupportedFmt; // is the format supported
|
||||
logic SupportedFmt2; // is the source format supported for fp -> fp
|
||||
logic FCvtIntD, FCvtIntM; // convert to integer opperation
|
||||
logic [`FCTRLW-1:0] ControlsD; // control signals
|
||||
logic FRegWriteD; // FP register write enable
|
||||
logic FDivStartD; // start division/sqrt
|
||||
logic FWriteIntD; // integer register write enable
|
||||
logic [2:0] OpCtrlD; // Select which opperation to do in each component
|
||||
logic [1:0] PostProcSelD; // select result in the post processing unit
|
||||
logic [1:0] FResSelD; // Select one of the results that finish in the memory stage
|
||||
logic [2:0] FrmD, FrmE; // FP rounding mode
|
||||
logic [P.FMTBITS-1:0] FmtD; // FP format
|
||||
logic [1:0] Fmt, Fmt2; // format - before possible reduction
|
||||
logic SupportedFmt; // is the format supported
|
||||
logic SupportedFmt2; // is the source format supported for fp -> fp
|
||||
logic FCvtIntD, FCvtIntM; // convert to integer opperation
|
||||
|
||||
// FPU Instruction Decoder
|
||||
assign Fmt = Funct7D[1:0];
|
||||
assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp
|
||||
|
||||
assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & `D_SUPPORTED) |
|
||||
(Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED));
|
||||
assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & `D_SUPPORTED) |
|
||||
(Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED));
|
||||
assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) |
|
||||
(Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED));
|
||||
assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) |
|
||||
(Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED));
|
||||
|
||||
// decode the instruction
|
||||
// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
|
||||
@ -98,19 +98,19 @@ module fctrl (
|
||||
ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
|
||||
else begin
|
||||
ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
|
||||
/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
|
||||
/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
|
||||
case(OpD)
|
||||
7'b0000111: case(Funct3D)
|
||||
3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
|
||||
3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
|
||||
3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
|
||||
3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
|
||||
3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
|
||||
3'b011: if (P.D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
|
||||
3'b100: if (P.Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
|
||||
3'b001: if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
|
||||
endcase
|
||||
7'b0100111: case(Funct3D)
|
||||
3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
|
||||
3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
|
||||
3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
|
||||
3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
|
||||
3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
|
||||
3'b011: if (P.D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
|
||||
3'b100: if (P.Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
|
||||
3'b001: if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
|
||||
endcase
|
||||
7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
|
||||
7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
|
||||
@ -139,9 +139,9 @@ module fctrl (
|
||||
7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
|
||||
ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass
|
||||
else if (Funct3D == 3'b000 & Rs2D == 5'b00000)
|
||||
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register
|
||||
7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
|
||||
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg
|
||||
ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w/d/h/q fp to int register
|
||||
7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
|
||||
ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w/d/h/q.x int to fp reg
|
||||
7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
|
||||
ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
|
||||
7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
|
||||
@ -227,14 +227,13 @@ module fctrl (
|
||||
// 10 - half
|
||||
// 11 - quad
|
||||
|
||||
if (`FPSIZES == 1)
|
||||
if (P.FPSIZES == 1)
|
||||
assign FmtD = 0;
|
||||
else if (`FPSIZES == 2)begin
|
||||
else if (P.FPSIZES == 2)begin
|
||||
logic [1:0] FmtTmp;
|
||||
assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
|
||||
assign FmtD = (`FMT == FmtTmp);
|
||||
end
|
||||
else if (`FPSIZES == 3|`FPSIZES == 4)
|
||||
assign FmtD = (P.FMT == FmtTmp);
|
||||
end else if (P.FPSIZES == 3|P.FPSIZES == 4)
|
||||
assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
|
||||
|
||||
// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
|
||||
@ -251,12 +250,9 @@ module fctrl (
|
||||
((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int
|
||||
((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
|
||||
|
||||
|
||||
|
||||
// Z - fma ops only
|
||||
assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
|
||||
|
||||
|
||||
// Final Res Sel:
|
||||
// fp int
|
||||
// 00 other cmp
|
||||
@ -313,19 +309,19 @@ module fctrl (
|
||||
assign Adr3D = InstrD[31:27];
|
||||
|
||||
// D/E pipleine register
|
||||
flopenrc #(13+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD},
|
||||
{FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE});
|
||||
flopenrc #(14+P.FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE,
|
||||
{FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD, ~IllegalFPUInstrD},
|
||||
{FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, FPUActiveE});
|
||||
flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
|
||||
flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
|
||||
flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
|
||||
|
||||
// Integer division on FPU divider
|
||||
if (`M_SUPPORTED & `IDIV_ON_FPU) assign IDivStartE = IntDivE;
|
||||
else assign IDivStartE = 0;
|
||||
if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE;
|
||||
else assign IDivStartE = 0;
|
||||
|
||||
// E/M pipleine register
|
||||
flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
|
||||
flopenrc #(13+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
|
||||
{FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE},
|
||||
{FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM});
|
||||
|
||||
|
||||
135
src/fpu/fcvt.sv
135
src/fpu/fcvt.sv
@ -1,4 +1,3 @@
|
||||
|
||||
///////////////////////////////////////////
|
||||
// fcvt.sv
|
||||
//
|
||||
@ -27,23 +26,21 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fcvt (
|
||||
input logic Xs, // input's sign
|
||||
input logic [`NE-1:0] Xe, // input's exponent
|
||||
input logic [`NF:0] Xm, // input's fraction
|
||||
input logic [`XLEN-1:0] Int, // integer input - from IEU
|
||||
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
|
||||
input logic ToInt, // is fp->int (since it's writting to the integer register)
|
||||
input logic XZero, // is the input zero
|
||||
input logic [`FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
|
||||
output logic [`NE:0] Ce, // the calculated expoent
|
||||
output logic [`LOGCVTLEN-1:0] ShiftAmt, // how much to shift by
|
||||
output logic ResSubnormUf,// does the result underflow or is subnormal
|
||||
output logic Cs, // the result's sign
|
||||
output logic IntZero, // is the integer zero?
|
||||
output logic [`CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder)
|
||||
module fcvt import cvw::*; #(parameter cvw_t P) (
|
||||
input logic Xs, // input's sign
|
||||
input logic [P.NE-1:0] Xe, // input's exponent
|
||||
input logic [P.NF:0] Xm, // input's fraction
|
||||
input logic [P.XLEN-1:0] Int, // integer input - from IEU
|
||||
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
|
||||
input logic ToInt, // is fp->int (since it's writting to the integer register)
|
||||
input logic XZero, // is the input zero
|
||||
input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
|
||||
output logic [P.NE:0] Ce, // the calculated expoent
|
||||
output logic [P.LOGCVTLEN-1:0] ShiftAmt, // how much to shift by
|
||||
output logic ResSubnormUf, // does the result underflow or is subnormal
|
||||
output logic Cs, // the result's sign
|
||||
output logic IntZero, // is the integer zero?
|
||||
output logic [P.CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder)
|
||||
);
|
||||
|
||||
// OpCtrls:
|
||||
@ -56,17 +53,16 @@ module fcvt (
|
||||
// bit 2 bit 1 bit 0
|
||||
// for example: signed long -> single floating point has the OpCode 101
|
||||
|
||||
logic [`FMTBITS-1:0] OutFmt; // format of the output
|
||||
logic [`XLEN-1:0] PosInt; // the positive integer input
|
||||
logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size
|
||||
logic [`NE-2:0] NewBias; // the bias of the final result
|
||||
logic [`NE-1:0] OldExp; // the old exponent
|
||||
logic Signed; // is the opperation with a signed integer?
|
||||
logic Int64; // is the integer 64 bits?
|
||||
logic IntToFp; // is the opperation an int->fp conversion?
|
||||
logic [`CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
|
||||
logic [`LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
|
||||
|
||||
logic [P.FMTBITS-1:0] OutFmt; // format of the output
|
||||
logic [P.XLEN-1:0] PosInt; // the positive integer input
|
||||
logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size
|
||||
logic [P.NE-2:0] NewBias; // the bias of the final result
|
||||
logic [P.NE-1:0] OldExp; // the old exponent
|
||||
logic Signed; // is the opperation with a signed integer?
|
||||
logic Int64; // is the integer 64 bits?
|
||||
logic IntToFp; // is the opperation an int->fp conversion?
|
||||
logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
|
||||
logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
|
||||
|
||||
// seperate OpCtrl for code readability
|
||||
assign Signed = OpCtrl[0];
|
||||
@ -76,12 +72,11 @@ module fcvt (
|
||||
// choose the ouptut format depending on the opperation
|
||||
// - fp -> fp: OpCtrl contains the percision of the output
|
||||
// - int -> fp: Fmt contains the percision of the output
|
||||
if (`FPSIZES == 2)
|
||||
assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == `FMT);
|
||||
else if (`FPSIZES == 3 | `FPSIZES == 4)
|
||||
if (P.FPSIZES == 2)
|
||||
assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == P.FMT);
|
||||
else if (P.FPSIZES == 3 | P.FPSIZES == 4)
|
||||
assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0];
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// negation
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
@ -89,7 +84,7 @@ module fcvt (
|
||||
// 2) trim the input to the proper size (kill the 32 most significant zeroes if needed)
|
||||
|
||||
assign PosInt = Cs ? -Int : Int;
|
||||
assign TrimInt = {{`XLEN-32{Int64}}, {32{1'b1}}} & PosInt;
|
||||
assign TrimInt = {{P.XLEN-32{Int64}}, {32{1'b1}}} & PosInt;
|
||||
assign IntZero = ~|TrimInt;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
@ -99,13 +94,13 @@ module fcvt (
|
||||
// choose the input to the leading zero counter i.e. priority encoder
|
||||
// int -> fp : | positive integer | 00000... (if needed) |
|
||||
// fp -> fp : | fraction | 00000... (if needed) |
|
||||
assign LzcInFull = IntToFp ? {TrimInt, {`CVTLEN-`XLEN+1{1'b0}}} :
|
||||
{Xm, {`CVTLEN-`NF{1'b0}}};
|
||||
assign LzcInFull = IntToFp ? {TrimInt, {P.CVTLEN-P.XLEN+1{1'b0}}} :
|
||||
{Xm, {P.CVTLEN-P.NF{1'b0}}};
|
||||
|
||||
// used as shifter input in postprocessor
|
||||
assign LzcIn = LzcInFull[`CVTLEN-1:0];
|
||||
assign LzcIn = LzcInFull[P.CVTLEN-1:0];
|
||||
|
||||
lzc #(`CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
|
||||
lzc #(P.CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// exp calculations
|
||||
@ -114,42 +109,41 @@ module fcvt (
|
||||
// Select the bias of the output
|
||||
// fp -> int : select 1
|
||||
// ??? -> fp : pick the new bias depending on the output format
|
||||
if (`FPSIZES == 1) begin
|
||||
assign NewBias = ToInt ? (`NE-1)'(1) : (`NE-1)'(`BIAS);
|
||||
if (P.FPSIZES == 1) begin
|
||||
assign NewBias = ToInt ? (P.NE-1)'(1) : (P.NE-1)'(P.BIAS);
|
||||
|
||||
end else if (`FPSIZES == 2) begin
|
||||
logic [`NE-2:0] NewBiasToFp;
|
||||
assign NewBiasToFp = OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
|
||||
assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp;
|
||||
end else if (P.FPSIZES == 2) begin
|
||||
logic [P.NE-2:0] NewBiasToFp;
|
||||
assign NewBiasToFp = OutFmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1);
|
||||
assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp;
|
||||
|
||||
end else if (`FPSIZES == 3) begin
|
||||
logic [`NE-2:0] NewBiasToFp;
|
||||
end else if (P.FPSIZES == 3) begin
|
||||
logic [P.NE-2:0] NewBiasToFp;
|
||||
always_comb
|
||||
case (OutFmt)
|
||||
`FMT: NewBiasToFp = (`NE-1)'(`BIAS);
|
||||
`FMT1: NewBiasToFp = (`NE-1)'(`BIAS1);
|
||||
`FMT2: NewBiasToFp = (`NE-1)'(`BIAS2);
|
||||
default: NewBiasToFp = {`NE-1{1'bx}};
|
||||
P.FMT: NewBiasToFp = (P.NE-1)'(P.BIAS);
|
||||
P.FMT1: NewBiasToFp = (P.NE-1)'(P.BIAS1);
|
||||
P.FMT2: NewBiasToFp = (P.NE-1)'(P.BIAS2);
|
||||
default: NewBiasToFp = {P.NE-1{1'bx}};
|
||||
endcase
|
||||
assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp;
|
||||
assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp;
|
||||
|
||||
end else if (`FPSIZES == 4) begin
|
||||
logic [`NE-2:0] NewBiasToFp;
|
||||
end else if (P.FPSIZES == 4) begin
|
||||
logic [P.NE-2:0] NewBiasToFp;
|
||||
always_comb
|
||||
case (OutFmt)
|
||||
2'h3: NewBiasToFp = (`NE-1)'(`Q_BIAS);
|
||||
2'h1: NewBiasToFp = (`NE-1)'(`D_BIAS);
|
||||
2'h0: NewBiasToFp = (`NE-1)'(`S_BIAS);
|
||||
2'h2: NewBiasToFp = (`NE-1)'(`H_BIAS);
|
||||
2'h3: NewBiasToFp = (P.NE-1)'(P.Q_BIAS);
|
||||
2'h1: NewBiasToFp = (P.NE-1)'(P.D_BIAS);
|
||||
2'h0: NewBiasToFp = (P.NE-1)'(P.S_BIAS);
|
||||
2'h2: NewBiasToFp = (P.NE-1)'(P.H_BIAS);
|
||||
endcase
|
||||
assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp;
|
||||
assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp;
|
||||
end
|
||||
|
||||
|
||||
// select the old exponent
|
||||
// int -> fp : largest bias + XLEN-1
|
||||
// fp -> ??? : XExp
|
||||
assign OldExp = IntToFp ? (`NE)'(`BIAS)+(`NE)'(`XLEN-1) : Xe;
|
||||
assign OldExp = IntToFp ? (P.NE)'(P.BIAS)+(P.NE)'(P.XLEN-1) : Xe;
|
||||
|
||||
// calculate CalcExp
|
||||
// fp -> fp :
|
||||
@ -159,13 +153,13 @@ module fcvt (
|
||||
// - correct the expoent when there is a normalization shift ( + LeadingZeros+1)
|
||||
// - the plus 1 is built into the leading zeros by counting the leading zeroes in the mantissa rather than the fraction
|
||||
// fp -> int : XExp - Largest Bias + 1 - (LeadingZeros+1)
|
||||
// | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp
|
||||
// | P.XLEN zeros | Mantissa | 0's if nessisary | << CalcExp
|
||||
// process:
|
||||
// - start
|
||||
// | `XLEN zeros | Mantissa | 0's if nessisary |
|
||||
// | P.XLEN zeros | Mantissa | 0's if nessisary |
|
||||
//
|
||||
// - shift left 1 (1)
|
||||
// | `XLEN-1 zeros |bit| frac | 0's if nessisary |
|
||||
// | P.XLEN-1 zeros |bit| frac | 0's if nessisary |
|
||||
// . <- binary point
|
||||
//
|
||||
// - shift left till unbiased exponent is 0 (XExp - Largest Bias)
|
||||
@ -185,14 +179,12 @@ module fcvt (
|
||||
// - newBias to make the biased exponent
|
||||
//
|
||||
// oldexp - biasold - LeadingZeros + newbias
|
||||
assign Ce = {1'b0, OldExp} - (`NE+1)'(`BIAS) - {{`NE-`LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
|
||||
|
||||
assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
|
||||
|
||||
// find if the result is dnormal or underflows
|
||||
// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
|
||||
// - can't underflow an integer to Fp conversion
|
||||
assign ResSubnormUf = (~|Ce | Ce[`NE])&~XZero&~IntToFp;
|
||||
|
||||
assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// shifter
|
||||
@ -211,10 +203,9 @@ module fcvt (
|
||||
// - this is a problem because the input to the lzc was the fraction rather than the mantissa
|
||||
// - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
|
||||
always_comb
|
||||
if(ToInt) ShiftAmt = Ce[`LOGCVTLEN-1:0]&{`LOGCVTLEN{~Ce[`NE]}};
|
||||
else if (ResSubnormUf) ShiftAmt = (`LOGCVTLEN)'(`NF-1)+Ce[`LOGCVTLEN-1:0];
|
||||
if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
|
||||
else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
|
||||
else ShiftAmt = LeadingZeros;
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// sign
|
||||
@ -227,9 +218,7 @@ module fcvt (
|
||||
// - otherwise: the floating point input's sign
|
||||
always_comb
|
||||
if(IntToFp)
|
||||
if(Int64) Cs = Int[`XLEN-1]&Signed;
|
||||
if(Int64) Cs = Int[P.XLEN-1]&Signed;
|
||||
else Cs = Int[31]&Signed;
|
||||
else Cs = Xs;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -26,74 +26,72 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrt(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic [`FMTBITS-1:0] FmtE,
|
||||
input logic XsE,
|
||||
input logic [`NF:0] XmE, YmE,
|
||||
input logic [`NE-1:0] XeE, YeE,
|
||||
input logic XInfE, YInfE,
|
||||
input logic XZeroE, YZeroE,
|
||||
input logic XNaNE, YNaNE,
|
||||
input logic FDivStartE, IDivStartE,
|
||||
input logic StallM,
|
||||
input logic FlushE,
|
||||
input logic SqrtE, SqrtM,
|
||||
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
input logic [2:0] Funct3E, Funct3M,
|
||||
input logic IntDivE, W64E,
|
||||
output logic DivStickyM,
|
||||
output logic FDivBusyE, IFDivStartE, FDivDoneE,
|
||||
output logic [`NE+1:0] QeM,
|
||||
output logic [`DIVb:0] QmM,
|
||||
output logic [`XLEN-1:0] FIntDivResultM
|
||||
module fdivsqrt import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic [P.FMTBITS-1:0] FmtE,
|
||||
input logic XsE,
|
||||
input logic [P.NF:0] XmE, YmE,
|
||||
input logic [P.NE-1:0] XeE, YeE,
|
||||
input logic XInfE, YInfE,
|
||||
input logic XZeroE, YZeroE,
|
||||
input logic XNaNE, YNaNE,
|
||||
input logic FDivStartE, IDivStartE,
|
||||
input logic StallM,
|
||||
input logic FlushE,
|
||||
input logic SqrtE, SqrtM,
|
||||
input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
input logic [2:0] Funct3E, Funct3M,
|
||||
input logic IntDivE, W64E,
|
||||
output logic DivStickyM,
|
||||
output logic FDivBusyE, IFDivStartE, FDivDoneE,
|
||||
output logic [P.NE+1:0] QeM,
|
||||
output logic [P.DIVb:0] QmM,
|
||||
output logic [P.XLEN-1:0] FIntDivResultM
|
||||
);
|
||||
|
||||
// Floating-point division and square root module, with optional integer division and remainder
|
||||
// Computes X/Y, sqrt(X), A/B, or A%B
|
||||
|
||||
logic [`DIVb+3:0] WS, WC; // Partial remainder components
|
||||
logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend)
|
||||
logic [`DIVb+3:0] D; // Iterator Divisor
|
||||
logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values
|
||||
logic [`DIVb+1:0] FirstC; // Step tracker
|
||||
logic Firstun; // Quotient selection
|
||||
logic WZeroE; // Early termination flag
|
||||
logic [`DURLEN-1:0] cycles; // FSM cycles
|
||||
logic SpecialCaseM; // Divide by zero, square root of negative, etc.
|
||||
logic DivStartE; // Enable signal for flops during stall
|
||||
logic [P.DIVb+3:0] WS, WC; // Partial remainder components
|
||||
logic [P.DIVb+3:0] X; // Iterator Initial Value (from dividend)
|
||||
logic [P.DIVb+3:0] D; // Iterator Divisor
|
||||
logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values
|
||||
logic [P.DIVb+1:0] FirstC; // Step tracker
|
||||
logic Firstun; // Quotient selection
|
||||
logic WZeroE; // Early termination flag
|
||||
logic [P.DURLEN-1:0] CyclesE; // FSM cycles
|
||||
logic SpecialCaseM; // Divide by zero, square root of negative, etc.
|
||||
logic DivStartE; // Enable signal for flops during stall
|
||||
|
||||
// Integer div/rem signals
|
||||
logic BZeroM; // Denominator is zero
|
||||
logic IntDivM; // Integer operation
|
||||
logic [`DIVBLEN:0] nM, mM; // Shift amounts
|
||||
logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
|
||||
logic [`XLEN-1:0] AM; // Original Numerator for postprocessor
|
||||
logic ISpecialCaseE; // Integer div/remainder special cases
|
||||
logic BZeroM; // Denominator is zero
|
||||
logic IntDivM; // Integer operation
|
||||
logic [P.DIVBLEN:0] nM, mM; // Shift amounts
|
||||
logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
|
||||
logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor
|
||||
logic ISpecialCaseE; // Integer div/remainder special cases
|
||||
|
||||
fdivsqrtpreproc fdivsqrtpreproc( // Preprocessor
|
||||
fdivsqrtpreproc #(P) fdivsqrtpreproc( // Preprocessor
|
||||
.clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
|
||||
.FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .cycles,
|
||||
.FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .CyclesE,
|
||||
// Int-specific
|
||||
.ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
|
||||
.BZeroM, .nM, .mM, .AM,
|
||||
.IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
|
||||
|
||||
fdivsqrtfsm fdivsqrtfsm( // FSM
|
||||
fdivsqrtfsm #(P) fdivsqrtfsm( // FSM
|
||||
.clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE,
|
||||
.FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM,
|
||||
.FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .cycles,
|
||||
.FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .CyclesE,
|
||||
// Int-specific
|
||||
.IDivStartE, .ISpecialCaseE, .IntDivE);
|
||||
|
||||
fdivsqrtiter fdivsqrtiter( // CSA Iterator
|
||||
fdivsqrtiter #(P) fdivsqrtiter( // CSA Iterator
|
||||
.clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D,
|
||||
.FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
|
||||
|
||||
fdivsqrtpostproc fdivsqrtpostproc( // Postprocessor
|
||||
fdivsqrtpostproc #(P) fdivsqrtpostproc( // Postprocessor
|
||||
.clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC,
|
||||
.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
|
||||
.QmM, .WZeroE, .DivStickyM,
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
///////////////////////////////////////////
|
||||
// fdivsqrt.sv
|
||||
// fdivsqrtcycles.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
|
||||
// Modified: 18 April 2022
|
||||
//
|
||||
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
|
||||
// Purpose: Determine number of cycles for divsqrt
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 13
|
||||
//
|
||||
@ -26,51 +26,50 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtcycles(
|
||||
input logic [`FMTBITS-1:0] FmtE,
|
||||
input logic SqrtE,
|
||||
input logic IntDivE,
|
||||
input logic [`DIVBLEN:0] nE,
|
||||
output logic [`DURLEN-1:0] cycles
|
||||
module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.FMTBITS-1:0] FmtE,
|
||||
input logic SqrtE,
|
||||
input logic IntDivE,
|
||||
input logic [P.DIVBLEN:0] nE,
|
||||
output logic [P.DURLEN-1:0] CyclesE
|
||||
);
|
||||
logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
|
||||
// DIVN = `NF+3
|
||||
logic [P.DURLEN+1:0] Nf, fbits; // number of fractional bits
|
||||
// DIVN = P.NF+3
|
||||
// NS = NF + 1
|
||||
// N = NS or NS+2 for div/sqrt.
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
if (`FPSIZES == 1)
|
||||
assign Nf = `NF;
|
||||
else if (`FPSIZES == 2)
|
||||
if (P.FPSIZES == 1)
|
||||
assign Nf = P.NF;
|
||||
else if (P.FPSIZES == 2)
|
||||
always_comb
|
||||
case (FmtE)
|
||||
1'b0: Nf = `NF1;
|
||||
1'b1: Nf = `NF;
|
||||
1'b0: Nf = P.NF1;
|
||||
1'b1: Nf = P.NF;
|
||||
endcase
|
||||
else if (`FPSIZES == 3)
|
||||
else if (P.FPSIZES == 3)
|
||||
always_comb
|
||||
case (FmtE)
|
||||
`FMT: Nf = `NF;
|
||||
`FMT1: Nf = `NF1;
|
||||
`FMT2: Nf = `NF2;
|
||||
P.FMT: Nf = P.NF;
|
||||
P.FMT1: Nf = P.NF1;
|
||||
P.FMT2: Nf = P.NF2;
|
||||
default: Nf = 'x; // shouldn't happen
|
||||
endcase
|
||||
else if (`FPSIZES == 4)
|
||||
else if (P.FPSIZES == 4)
|
||||
always_comb
|
||||
case(FmtE)
|
||||
`S_FMT: Nf = `S_NF;
|
||||
`D_FMT: Nf = `D_NF;
|
||||
`H_FMT: Nf = `H_NF;
|
||||
`Q_FMT: Nf = `Q_NF;
|
||||
P.S_FMT: Nf = P.S_NF;
|
||||
P.D_FMT: Nf = P.D_NF;
|
||||
P.H_FMT: Nf = P.H_NF;
|
||||
P.Q_FMT: Nf = P.Q_NF;
|
||||
endcase
|
||||
|
||||
always_comb begin
|
||||
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
|
||||
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
|
||||
if (`IDIV_ON_FPU) cycles = IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
|
||||
else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
|
||||
else fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
|
||||
if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
|
||||
else CyclesE = (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
|
||||
end
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
@ -26,49 +26,47 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtexpcalc(
|
||||
input logic [`FMTBITS-1:0] Fmt,
|
||||
input logic [`NE-1:0] Xe, Ye,
|
||||
input logic Sqrt,
|
||||
input logic XZero,
|
||||
input logic [`DIVBLEN:0] ell, m,
|
||||
output logic [`NE+1:0] Qe
|
||||
module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.FMTBITS-1:0] Fmt,
|
||||
input logic [P.NE-1:0] Xe, Ye,
|
||||
input logic Sqrt,
|
||||
input logic XZero,
|
||||
input logic [P.DIVBLEN:0] ell, m,
|
||||
output logic [P.NE+1:0] Qe
|
||||
);
|
||||
logic [`NE-2:0] Bias;
|
||||
logic [`NE+1:0] SXExp;
|
||||
logic [`NE+1:0] SExp;
|
||||
logic [`NE+1:0] DExp;
|
||||
logic [P.NE-2:0] Bias;
|
||||
logic [P.NE+1:0] SXExp;
|
||||
logic [P.NE+1:0] SExp;
|
||||
logic [P.NE+1:0] DExp;
|
||||
|
||||
if (`FPSIZES == 1) begin
|
||||
assign Bias = (`NE-1)'(`BIAS);
|
||||
if (P.FPSIZES == 1) begin
|
||||
assign Bias = (P.NE-1)'(P.BIAS);
|
||||
|
||||
end else if (`FPSIZES == 2) begin
|
||||
assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
|
||||
end else if (P.FPSIZES == 2) begin
|
||||
assign Bias = Fmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1);
|
||||
|
||||
end else if (`FPSIZES == 3) begin
|
||||
end else if (P.FPSIZES == 3) begin
|
||||
always_comb
|
||||
case (Fmt)
|
||||
`FMT: Bias = (`NE-1)'(`BIAS);
|
||||
`FMT1: Bias = (`NE-1)'(`BIAS1);
|
||||
`FMT2: Bias = (`NE-1)'(`BIAS2);
|
||||
P.FMT: Bias = (P.NE-1)'(P.BIAS);
|
||||
P.FMT1: Bias = (P.NE-1)'(P.BIAS1);
|
||||
P.FMT2: Bias = (P.NE-1)'(P.BIAS2);
|
||||
default: Bias = 'x;
|
||||
endcase
|
||||
|
||||
end else if (`FPSIZES == 4) begin
|
||||
end else if (P.FPSIZES == 4) begin
|
||||
always_comb
|
||||
case (Fmt)
|
||||
2'h3: Bias = (`NE-1)'(`Q_BIAS);
|
||||
2'h1: Bias = (`NE-1)'(`D_BIAS);
|
||||
2'h0: Bias = (`NE-1)'(`S_BIAS);
|
||||
2'h2: Bias = (`NE-1)'(`H_BIAS);
|
||||
2'h3: Bias = (P.NE-1)'(P.Q_BIAS);
|
||||
2'h1: Bias = (P.NE-1)'(P.D_BIAS);
|
||||
2'h0: Bias = (P.NE-1)'(P.S_BIAS);
|
||||
2'h2: Bias = (P.NE-1)'(P.H_BIAS);
|
||||
endcase
|
||||
end
|
||||
assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
|
||||
assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
|
||||
assign SXExp = {2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - (P.NE+2)'(P.BIAS);
|
||||
assign SExp = {SXExp[P.NE+1], SXExp[P.NE+1:1]} + {2'b0, Bias};
|
||||
|
||||
// correct exponent for subnormal input's normalization shifts
|
||||
assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias});
|
||||
assign DExp = ({2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(P.NE+1-P.DIVBLEN){1'b0}}, m} + {3'b0, Bias});
|
||||
assign Qe = Sqrt ? SExp : DExp;
|
||||
endmodule
|
||||
|
||||
@ -26,21 +26,18 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtfgen2 (
|
||||
input logic up, uz,
|
||||
input logic [`DIVb+3:0] C, U, UM,
|
||||
output logic [`DIVb+3:0] F
|
||||
module fdivsqrtfgen2 import cvw::*; #(parameter cvw_t P) (
|
||||
input logic up, uz,
|
||||
input logic [P.DIVb+3:0] C, U, UM,
|
||||
output logic [P.DIVb+3:0] F
|
||||
);
|
||||
logic [`DIVb+3:0] FP, FN, FZ;
|
||||
logic [P.DIVb+3:0] FP, FN, FZ;
|
||||
|
||||
// Generate for both positive and negative bits
|
||||
assign FP = ~(U << 1) & C;
|
||||
assign FN = (UM << 1) | (C & ~(C << 2));
|
||||
assign FZ = '0;
|
||||
|
||||
|
||||
always_comb // Choose which adder input will be used
|
||||
if (up) F = FP;
|
||||
else if (uz) F = FZ;
|
||||
|
||||
@ -26,14 +26,12 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtfgen4 (
|
||||
input logic [3:0] udigit,
|
||||
input logic [`DIVb+3:0] C, U, UM,
|
||||
output logic [`DIVb+3:0] F
|
||||
module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [3:0] udigit,
|
||||
input logic [P.DIVb+3:0] C, U, UM,
|
||||
output logic [P.DIVb+3:0] F
|
||||
);
|
||||
logic [`DIVb+3:0] F2, F1, F0, FN1, FN2;
|
||||
logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2;
|
||||
|
||||
// Generate for both positive and negative bits
|
||||
assign F2 = (~U << 2) & (C << 2);
|
||||
@ -49,4 +47,4 @@ module fdivsqrtfgen4 (
|
||||
else if (udigit[1]) F = FN1;
|
||||
else if (udigit[0]) F = FN2;
|
||||
else F = F0;
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
@ -26,39 +26,37 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtfsm(
|
||||
input logic clk, reset,
|
||||
input logic XInfE, YInfE,
|
||||
input logic XZeroE, YZeroE,
|
||||
input logic XNaNE, YNaNE,
|
||||
input logic FDivStartE, IDivStartE,
|
||||
input logic XsE, WZeroE,
|
||||
input logic SqrtE,
|
||||
input logic StallM, FlushE,
|
||||
input logic IntDivE,
|
||||
input logic ISpecialCaseE,
|
||||
input logic [`DURLEN-1:0] cycles,
|
||||
output logic IFDivStartE,
|
||||
output logic FDivBusyE, FDivDoneE,
|
||||
output logic SpecialCaseM
|
||||
module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk, reset,
|
||||
input logic XInfE, YInfE,
|
||||
input logic XZeroE, YZeroE,
|
||||
input logic XNaNE, YNaNE,
|
||||
input logic FDivStartE, IDivStartE,
|
||||
input logic XsE, WZeroE,
|
||||
input logic SqrtE,
|
||||
input logic StallM, FlushE,
|
||||
input logic IntDivE,
|
||||
input logic ISpecialCaseE,
|
||||
input logic [P.DURLEN-1:0] CyclesE,
|
||||
output logic IFDivStartE,
|
||||
output logic FDivBusyE, FDivDoneE,
|
||||
output logic SpecialCaseM
|
||||
);
|
||||
|
||||
typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
|
||||
statetype state;
|
||||
|
||||
logic SpecialCaseE, FSpecialCaseE;
|
||||
logic [`DURLEN-1:0] step;
|
||||
logic [P.DURLEN-1:0] step;
|
||||
|
||||
// FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
|
||||
assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
|
||||
assign IFDivStartE = (FDivStartE | (IDivStartE & P.IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
|
||||
assign FDivDoneE = (state == DONE);
|
||||
assign FDivBusyE = (state == BUSY) | IFDivStartE;
|
||||
|
||||
// terminate immediately on special cases
|
||||
assign FSpecialCaseE = XZeroE | | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
|
||||
if (`IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
|
||||
assign FSpecialCaseE = XZeroE | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
|
||||
if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
|
||||
else assign SpecialCaseE = FSpecialCaseE;
|
||||
flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
|
||||
|
||||
@ -66,8 +64,7 @@ module fdivsqrtfsm(
|
||||
if (reset | FlushE) begin
|
||||
state <= #1 IDLE;
|
||||
end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
|
||||
// end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
|
||||
step <= cycles;
|
||||
step <= CyclesE;
|
||||
if (SpecialCaseE) state <= #1 DONE;
|
||||
else state <= #1 BUSY;
|
||||
end else if (state == BUSY) begin
|
||||
@ -79,4 +76,4 @@ module fdivsqrtfsm(
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
||||
@ -26,38 +26,36 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtiter(
|
||||
input logic clk,
|
||||
input logic IFDivStartE,
|
||||
input logic FDivBusyE,
|
||||
input logic SqrtE,
|
||||
input logic [`DIVb+3:0] X, D,
|
||||
output logic [`DIVb:0] FirstU, FirstUM,
|
||||
output logic [`DIVb+1:0] FirstC,
|
||||
output logic Firstun,
|
||||
output logic [`DIVb+3:0] FirstWS, FirstWC
|
||||
module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic IFDivStartE,
|
||||
input logic FDivBusyE,
|
||||
input logic SqrtE,
|
||||
input logic [P.DIVb+3:0] X, D,
|
||||
output logic [P.DIVb:0] FirstU, FirstUM,
|
||||
output logic [P.DIVb+1:0] FirstC,
|
||||
output logic Firstun,
|
||||
output logic [P.DIVb+3:0] FirstWS, FirstWC
|
||||
);
|
||||
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
logic [`DIVb+3:0] WSNext[`DIVCOPIES-1:0]; // Q4.b
|
||||
logic [`DIVb+3:0] WCNext[`DIVCOPIES-1:0]; // Q4.b
|
||||
logic [`DIVb+3:0] WS[`DIVCOPIES:0]; // Q4.b
|
||||
logic [`DIVb+3:0] WC[`DIVCOPIES:0]; // Q4.b
|
||||
logic [`DIVb:0] U[`DIVCOPIES:0]; // U1.b
|
||||
logic [`DIVb:0] UM[`DIVCOPIES:0]; // U1.b
|
||||
logic [`DIVb:0] UNext[`DIVCOPIES-1:0]; // U1.b
|
||||
logic [`DIVb:0] UMNext[`DIVCOPIES-1:0]; // U1.b
|
||||
logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b
|
||||
logic [`DIVb+1:0] initC; // Q2.b
|
||||
logic [`DIVCOPIES-1:0] un;
|
||||
logic [P.DIVb+3:0] WSNext[P.DIVCOPIES-1:0]; // Q4.b
|
||||
logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.b
|
||||
logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.b
|
||||
logic [P.DIVb+3:0] WC[P.DIVCOPIES:0]; // Q4.b
|
||||
logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.b
|
||||
logic [P.DIVb:0] UM[P.DIVCOPIES:0]; // U1.b
|
||||
logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.b
|
||||
logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.b
|
||||
logic [P.DIVb+1:0] C[P.DIVCOPIES:0]; // Q2.b
|
||||
logic [P.DIVb+1:0] initC; // Q2.b
|
||||
logic [P.DIVCOPIES-1:0] un;
|
||||
|
||||
logic [`DIVb+3:0] WSN, WCN; // Q4.b
|
||||
logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.b
|
||||
logic [`DIVb+1:0] NextC;
|
||||
logic [`DIVb:0] UMux, UMMux;
|
||||
logic [`DIVb:0] initU, initUM;
|
||||
logic [P.DIVb+3:0] WSN, WCN; // Q4.b
|
||||
logic [P.DIVb+3:0] DBar, D2, DBar2; // Q4.b
|
||||
logic [P.DIVb+1:0] NextC;
|
||||
logic [P.DIVb:0] UMux, UMMux;
|
||||
logic [P.DIVb:0] initU, initUM;
|
||||
/* verilator lint_on UNOPTFLAT */
|
||||
|
||||
// Top Muxes and Registers
|
||||
@ -65,37 +63,37 @@ module fdivsqrtiter(
|
||||
// Otherwise, the divisor is retained and the residual and result
|
||||
// are fed back for the next iteration.
|
||||
|
||||
// Residual WS/SC registers/initializaiton mux
|
||||
mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, IFDivStartE, WSN);
|
||||
mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, IFDivStartE, WCN);
|
||||
flopen #(`DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
|
||||
flopen #(`DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
|
||||
// Residual WS/SC registers/initialization mux
|
||||
mux2 #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
|
||||
mux2 #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
|
||||
flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
|
||||
flopen #(P.DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
|
||||
|
||||
// UOTFC Result U and UM registers/initialization mux
|
||||
// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
|
||||
assign initU = {SqrtE, {(`DIVb){1'b0}}};
|
||||
assign initUM = {~SqrtE, {(`DIVb){1'b0}}};
|
||||
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux);
|
||||
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
|
||||
flopen #(`DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]);
|
||||
flopen #(`DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
|
||||
assign initU = {SqrtE, {(P.DIVb){1'b0}}};
|
||||
assign initUM = {~SqrtE, {(P.DIVb){1'b0}}};
|
||||
mux2 #(P.DIVb+1) Umux(UNext[P.DIVCOPIES-1], initU, IFDivStartE, UMux);
|
||||
mux2 #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux);
|
||||
flopen #(P.DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]);
|
||||
flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
|
||||
|
||||
// C register/initialization mux
|
||||
// Initialize C to -1 for sqrt and -R for division
|
||||
logic [1:0] initCUpper;
|
||||
if(`RADIX == 4) begin
|
||||
if(P.RADIX == 4) begin
|
||||
mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
|
||||
end else begin
|
||||
mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
|
||||
end
|
||||
|
||||
assign initC = {initCUpper, {`DIVb{1'b0}}};
|
||||
mux2 #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC);
|
||||
flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
|
||||
assign initC = {initCUpper, {P.DIVb{1'b0}}};
|
||||
mux2 #(P.DIVb+2) cmux(C[P.DIVCOPIES], initC, IFDivStartE, NextC);
|
||||
flopen #(P.DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
|
||||
|
||||
// Divisor Selections
|
||||
assign DBar = ~D; // for -D
|
||||
if(`RADIX == 4) begin : d2
|
||||
if(P.RADIX == 4) begin : d2
|
||||
assign D2 = D << 1; // for 2D, only used in R4
|
||||
assign DBar2 = ~D2; // for -2D, only used in R4
|
||||
end
|
||||
@ -103,15 +101,15 @@ module fdivsqrtiter(
|
||||
// k=DIVCOPIES of the recurrence logic
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
|
||||
if (`RADIX == 2) begin: stage
|
||||
fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE,
|
||||
for(i=0; $unsigned(i)<P.DIVCOPIES; i++) begin : iterations
|
||||
if (P.RADIX == 2) begin: stage
|
||||
fdivsqrtstage2 #(P) fdivsqrtstage(.D, .DBar, .SqrtE,
|
||||
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
||||
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
||||
end else begin: stage
|
||||
logic j1;
|
||||
assign j1 = (i == 0 & ~C[0][`DIVb-1]);
|
||||
fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
|
||||
assign j1 = (i == 0 & ~C[0][P.DIVb-1]);
|
||||
fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
|
||||
.WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
|
||||
.C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
|
||||
end
|
||||
|
||||
@ -26,51 +26,49 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtpostproc(
|
||||
input logic clk, reset,
|
||||
input logic StallM,
|
||||
input logic [`DIVb+3:0] WS, WC,
|
||||
input logic [`DIVb+3:0] D,
|
||||
input logic [`DIVb:0] FirstU, FirstUM,
|
||||
input logic [`DIVb+1:0] FirstC,
|
||||
input logic SqrtE,
|
||||
input logic Firstun, SqrtM, SpecialCaseM, NegQuotM,
|
||||
input logic [`XLEN-1:0] AM,
|
||||
input logic RemOpM, ALTBM, BZeroM, AsM, W64M,
|
||||
input logic [`DIVBLEN:0] nM, mM,
|
||||
output logic [`DIVb:0] QmM,
|
||||
output logic WZeroE,
|
||||
output logic DivStickyM,
|
||||
output logic [`XLEN-1:0] FIntDivResultM
|
||||
module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk, reset,
|
||||
input logic StallM,
|
||||
input logic [P.DIVb+3:0] WS, WC,
|
||||
input logic [P.DIVb+3:0] D,
|
||||
input logic [P.DIVb:0] FirstU, FirstUM,
|
||||
input logic [P.DIVb+1:0] FirstC,
|
||||
input logic SqrtE,
|
||||
input logic Firstun, SqrtM, SpecialCaseM, NegQuotM,
|
||||
input logic [P.XLEN-1:0] AM,
|
||||
input logic RemOpM, ALTBM, BZeroM, AsM, W64M,
|
||||
input logic [P.DIVBLEN:0] nM, mM,
|
||||
output logic [P.DIVb:0] QmM,
|
||||
output logic WZeroE,
|
||||
output logic DivStickyM,
|
||||
output logic [P.XLEN-1:0] FIntDivResultM
|
||||
);
|
||||
|
||||
logic [`DIVb+3:0] W, Sum;
|
||||
logic [`DIVb:0] PreQmM;
|
||||
logic NegStickyM;
|
||||
logic weq0E, WZeroM;
|
||||
logic [`XLEN-1:0] IntDivResultM;
|
||||
logic [P.DIVb+3:0] W, Sum;
|
||||
logic [P.DIVb:0] PreQmM;
|
||||
logic NegStickyM;
|
||||
logic weq0E, WZeroM;
|
||||
logic [P.XLEN-1:0] IntDivResultM;
|
||||
|
||||
//////////////////////////
|
||||
// Execute Stage: Detect early termination for an exact result
|
||||
//////////////////////////
|
||||
|
||||
// check for early termination on an exact result.
|
||||
aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0E);
|
||||
aplusbeq0 #(P.DIVb+4) wspluswceq0(WS, WC, weq0E);
|
||||
|
||||
if (`RADIX == 2) begin: R2EarlyTerm
|
||||
logic [`DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
|
||||
logic [`DIVb+2:0] FirstK;
|
||||
if (P.RADIX == 2) begin: R2EarlyTerm
|
||||
logic [P.DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
|
||||
logic [P.DIVb+2:0] FirstK;
|
||||
logic wfeq0E;
|
||||
logic [`DIVb+3:0] WCF, WSF;
|
||||
logic [P.DIVb+3:0] WCF, WSF;
|
||||
|
||||
assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
|
||||
assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0}; // F for square root
|
||||
assign FZeroSqrtE = {FirstUM[P.DIVb], FirstUM, 2'b0} | {FirstK,1'b0}; // F for square root
|
||||
assign FZeroDivE = D << 1; // F for divide
|
||||
mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
|
||||
csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
|
||||
aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
|
||||
mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
|
||||
csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
|
||||
aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
|
||||
assign WZeroE = weq0E|(wfeq0E & Firstun);
|
||||
end else begin
|
||||
assign WZeroE = weq0E;
|
||||
@ -91,27 +89,27 @@ module fdivsqrtpostproc(
|
||||
|
||||
// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
|
||||
assign Sum = WC + WS;
|
||||
assign NegStickyM = Sum[`DIVb+3];
|
||||
mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
|
||||
mux2 #(`DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
|
||||
assign NegStickyM = Sum[P.DIVb+3];
|
||||
mux2 #(P.DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
|
||||
mux2 #(P.DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
|
||||
|
||||
// Integer quotient or remainder correctoin, normalization, and special cases
|
||||
if (`IDIV_ON_FPU) begin:intpostproc // Int supported
|
||||
logic [`DIVBLEN:0] NormShiftM;
|
||||
logic [`DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
|
||||
logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
|
||||
if (P.IDIV_ON_FPU) begin:intpostproc // Int supported
|
||||
logic [P.DIVBLEN:0] NormShiftM;
|
||||
logic [P.DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
|
||||
logic signed [P.DIVb+3:0] PreResultM, PreIntResultM;
|
||||
|
||||
assign W = $signed(Sum) >>> `LOGR;
|
||||
assign W = $signed(Sum) >>> P.LOGR;
|
||||
assign UnsignedQuotM = {3'b000, PreQmM};
|
||||
|
||||
// Integer remainder: sticky and sign correction muxes
|
||||
mux2 #(`DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
|
||||
mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
|
||||
mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
|
||||
mux2 #(P.DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
|
||||
mux2 #(P.DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
|
||||
mux2 #(P.DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
|
||||
|
||||
// Select quotient or remainder and do normalization shift
|
||||
mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
|
||||
mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
|
||||
mux2 #(P.DIVBLEN+1) normshiftmux(((P.DIVBLEN+1)'(P.DIVb) - (nM * (P.DIVBLEN+1)'(P.LOGR))), (mM + (P.DIVBLEN+1)'(P.DIVa)), RemOpM, NormShiftM);
|
||||
mux2 #(P.DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
|
||||
assign PreIntResultM = $signed(PreResultM >>> NormShiftM);
|
||||
|
||||
// special case logic
|
||||
@ -119,18 +117,18 @@ module fdivsqrtpostproc(
|
||||
always_comb
|
||||
if (BZeroM) begin // Divide by zero
|
||||
if (RemOpM) IntDivResultM = AM;
|
||||
else IntDivResultM = {(`XLEN){1'b1}};
|
||||
else IntDivResultM = {(P.XLEN){1'b1}};
|
||||
end else if (ALTBM) begin // Numerator is zero
|
||||
if (RemOpM) IntDivResultM = AM;
|
||||
else IntDivResultM = '0;
|
||||
end else IntDivResultM = PreIntResultM[`XLEN-1:0];
|
||||
end else IntDivResultM = PreIntResultM[P.XLEN-1:0];
|
||||
|
||||
// sign extend result for W64
|
||||
if (`XLEN==64) begin
|
||||
mux2 #(64) resmux(IntDivResultM[`XLEN-1:0],
|
||||
{{(`XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
|
||||
if (P.XLEN==64) begin
|
||||
mux2 #(64) resmux(IntDivResultM[P.XLEN-1:0],
|
||||
{{(P.XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
|
||||
W64M, FIntDivResultM);
|
||||
end else
|
||||
assign FIntDivResultM = IntDivResultM[`XLEN-1:0];
|
||||
assign FIntDivResultM = IntDivResultM[P.XLEN-1:0];
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -26,157 +26,183 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module fdivsqrtpreproc (
|
||||
input logic clk,
|
||||
input logic IFDivStartE,
|
||||
input logic [`NF:0] Xm, Ym,
|
||||
input logic [`NE-1:0] Xe, Ye,
|
||||
input logic [`FMTBITS-1:0] FmtE,
|
||||
input logic SqrtE,
|
||||
input logic XZeroE,
|
||||
input logic [2:0] Funct3E,
|
||||
output logic [`NE+1:0] QeM,
|
||||
output logic [`DIVb+3:0] X, D,
|
||||
module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic IFDivStartE,
|
||||
input logic [P.NF:0] Xm, Ym,
|
||||
input logic [P.NE-1:0] Xe, Ye,
|
||||
input logic [P.FMTBITS-1:0] FmtE,
|
||||
input logic SqrtE,
|
||||
input logic XZeroE,
|
||||
input logic [2:0] Funct3E,
|
||||
output logic [P.NE+1:0] QeM,
|
||||
output logic [P.DIVb+3:0] X, D,
|
||||
// Int-specific
|
||||
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
input logic IntDivE, W64E,
|
||||
output logic ISpecialCaseE,
|
||||
output logic [`DURLEN-1:0] cycles,
|
||||
output logic [`DIVBLEN:0] nM, mM,
|
||||
output logic NegQuotM, ALTBM, IntDivM, W64M,
|
||||
output logic AsM, BZeroM,
|
||||
output logic [`XLEN-1:0] AM
|
||||
input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
|
||||
input logic IntDivE, W64E,
|
||||
output logic ISpecialCaseE,
|
||||
output logic [P.DURLEN-1:0] CyclesE,
|
||||
output logic [P.DIVBLEN:0] nM, mM,
|
||||
output logic NegQuotM, ALTBM, IntDivM, W64M,
|
||||
output logic AsM, BZeroM,
|
||||
output logic [P.XLEN-1:0] AM
|
||||
);
|
||||
|
||||
logic [`DIVb-1:0] XPreproc, DPreproc;
|
||||
logic [`DIVb:0] PreSqrtX;
|
||||
logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
|
||||
logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
|
||||
logic [`DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
|
||||
logic [`DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs
|
||||
logic NumerZeroE; // Numerator is zero (X or A)
|
||||
logic AZeroE, BZeroE; // A or B is Zero for integer division
|
||||
logic signedDiv; // signed division
|
||||
logic NegQuotE; // Integer quotient is negative
|
||||
logic AsE, BsE; // Signs of integer inputs
|
||||
logic [`XLEN-1:0] AE; // input A after W64 adjustment
|
||||
logic [P.DIVb-1:0] Xfract, Dfract;
|
||||
logic [P.DIVb:0] PreSqrtX;
|
||||
logic [P.DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
|
||||
logic [P.NE+1:0] QeE; // Quotient Exponent (FP only)
|
||||
logic [P.DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
|
||||
logic [P.DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs
|
||||
logic NumerZeroE; // Numerator is zero (X or A)
|
||||
logic AZeroE, BZeroE; // A or B is Zero for integer division
|
||||
logic SignedDivE; // signed division
|
||||
logic NegQuotE; // Integer quotient is negative
|
||||
logic AsE, BsE; // Signs of integer inputs
|
||||
logic [P.XLEN-1:0] AE; // input A after W64 adjustment
|
||||
logic ALTBE;
|
||||
|
||||
if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
|
||||
logic [`XLEN-1:0] BE, PosA, PosB;
|
||||
//////////////////////////////////////////////////////
|
||||
// Integer Preprocessing
|
||||
//////////////////////////////////////////////////////
|
||||
|
||||
if (P.IDIV_ON_FPU) begin:intpreproc // Int Supported
|
||||
logic [P.XLEN-1:0] BE, PosA, PosB;
|
||||
|
||||
// Extract inputs, signs, zero, depending on W64 mode if applicable
|
||||
assign signedDiv = ~Funct3E[0];
|
||||
assign SignedDivE = ~Funct3E[0];
|
||||
|
||||
// Source handling
|
||||
if (`XLEN==64) begin // 64-bit, supports W64
|
||||
mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & signedDiv}}, ForwardedSrcAE[31:0]}, W64E, AE);
|
||||
mux2 #(64) bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & signedDiv}}, ForwardedSrcBE[31:0]}, W64E, BE);
|
||||
if (P.XLEN==64) begin // 64-bit, supports W64
|
||||
mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & SignedDivE}}, ForwardedSrcAE[31:0]}, W64E, AE);
|
||||
mux2 #(64) bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & SignedDivE}}, ForwardedSrcBE[31:0]}, W64E, BE);
|
||||
end else begin // 32 bits only
|
||||
assign AE = ForwardedSrcAE;
|
||||
assign BE = ForwardedSrcBE;
|
||||
end
|
||||
assign AZeroE = ~(|AE);
|
||||
assign BZeroE = ~(|BE);
|
||||
assign AsE = AE[`XLEN-1] & signedDiv;
|
||||
assign BsE = BE[`XLEN-1] & signedDiv;
|
||||
assign AsE = AE[P.XLEN-1] & SignedDivE;
|
||||
assign BsE = BE[P.XLEN-1] & SignedDivE;
|
||||
assign NegQuotE = AsE ^ BsE; // Integer Quotient is negative
|
||||
|
||||
// Force integer inputs to be postiive
|
||||
mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
|
||||
mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
|
||||
mux2 #(P.XLEN) posamux(AE, -AE, AsE, PosA);
|
||||
mux2 #(P.XLEN) posbmux(BE, -BE, BsE, PosB);
|
||||
|
||||
// Select integer or floating point inputs
|
||||
mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFX);
|
||||
mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFD);
|
||||
|
||||
|
||||
mux2 #(P.DIVb) ifxmux({Xm, {(P.DIVb-P.NF-1){1'b0}}}, {PosA, {(P.DIVb-P.XLEN){1'b0}}}, IntDivE, IFX);
|
||||
mux2 #(P.DIVb) ifdmux({Ym, {(P.DIVb-P.NF-1){1'b0}}}, {PosB, {(P.DIVb-P.XLEN){1'b0}}}, IntDivE, IFD);
|
||||
mux2 #(1) numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
|
||||
end else begin // Int not supported
|
||||
assign IFX = {Xm, {(`DIVb-`NF-1){1'b0}}};
|
||||
assign IFD = {Ym, {(`DIVb-`NF-1){1'b0}}};
|
||||
assign IFX = {Xm, {(P.DIVb-P.NF-1){1'b0}}};
|
||||
assign IFD = {Ym, {(P.DIVb-P.NF-1){1'b0}}};
|
||||
assign NumerZeroE = XZeroE;
|
||||
end
|
||||
|
||||
//////////////////////////////////////////////////////
|
||||
// Integer & FP leading zero and normalization shift
|
||||
//////////////////////////////////////////////////////
|
||||
|
||||
// count leading zeros for Subnorm FP and to normalize integer inputs
|
||||
lzc #(`DIVb) lzcX (IFX, ell);
|
||||
lzc #(`DIVb) lzcY (IFD, mE);
|
||||
lzc #(P.DIVb) lzcX (IFX, ell);
|
||||
lzc #(P.DIVb) lzcY (IFD, mE);
|
||||
|
||||
// Normalization shift: shift off leading one
|
||||
assign XPreproc = (IFX << ell) << 1;
|
||||
assign DPreproc = (IFD << mE) << 1;
|
||||
assign Xfract = (IFX << ell) << 1;
|
||||
assign Dfract = (IFD << mE) << 1;
|
||||
|
||||
// append leading 1 (for nonzero inputs)
|
||||
// shift square root to be in range [1/4, 1)
|
||||
// Normalized numbers are shifted right by 1 if the exponent is odd
|
||||
// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
|
||||
mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
|
||||
assign DivX = {3'b000, ~NumerZeroE, XPreproc};
|
||||
// *** CT: move to fdivsqrtintpreshift
|
||||
|
||||
// Divisior register
|
||||
flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D);
|
||||
//////////////////////////////////////////////////////
|
||||
// Integer Right Shift to digit boundary
|
||||
// Determine DivXShifted (X shifted to digit boundary)
|
||||
// and nE (number of fractional digits)
|
||||
//////////////////////////////////////////////////////
|
||||
|
||||
// ***CT: factor out fdivsqrtcycles
|
||||
if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
|
||||
logic [`DIVBLEN:0] ZeroDiff, p;
|
||||
logic ALTBE;
|
||||
if (P.IDIV_ON_FPU) begin:intrightshift // Int Supported
|
||||
logic [P.DIVBLEN:0] ZeroDiff, p;
|
||||
|
||||
// calculate number of fractional bits p
|
||||
assign ZeroDiff = mE - ell; // Difference in number of leading zeros
|
||||
assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B (A has more leading zeros)
|
||||
mux2 #(`DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
|
||||
assign ALTBE = ZeroDiff[P.DIVBLEN]; // A less than B (A has more leading zeros)
|
||||
mux2 #(P.DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);
|
||||
|
||||
// Integer special cases (terminate immediately)
|
||||
assign ISpecialCaseE = BZeroE | ALTBE;
|
||||
|
||||
/* verilator lint_off WIDTH */
|
||||
// calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
|
||||
|
||||
if (`LOGRK > 0) begin // more than 1 bit per cycle
|
||||
logic [`LOGRK-1:0] IntTrunc, RightShiftX;
|
||||
logic [`DIVBLEN:0] TotalIntBits, IntSteps;
|
||||
|
||||
assign TotalIntBits = `LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
|
||||
assign IntTrunc = TotalIntBits % `RK; // Truncation check for ceiling operator
|
||||
assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc; // Number of steps for int div
|
||||
assign nE = (IntSteps * `DIVCOPIES) - 1; // Fractional digits
|
||||
assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK); // Right shift amount
|
||||
if (P.LOGRK > 0) begin // more than 1 bit per cycle
|
||||
logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
|
||||
logic [P.DIVBLEN:0] TotalIntBits, IntSteps;
|
||||
/* verilator lint_off WIDTH */
|
||||
assign TotalIntBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
|
||||
assign IntTrunc = TotalIntBits % P.RK; // Truncation check for ceiling operator
|
||||
assign IntSteps = (TotalIntBits >> P.LOGRK) + |IntTrunc; // Number of steps for int div
|
||||
assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits
|
||||
assign RightShiftX = P.RK - 1 - ((TotalIntBits - 1) % P.RK); // Right shift amount
|
||||
assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps
|
||||
/* verilator lint_on WIDTH */
|
||||
end else begin // radix 2 1 copy doesn't require shifting
|
||||
assign nE = p;
|
||||
assign DivXShifted = DivX;
|
||||
end
|
||||
/* verilator lint_on WIDTH */
|
||||
end else begin
|
||||
assign ISpecialCaseE = 0;
|
||||
end
|
||||
|
||||
// Selet integer or floating-point operands
|
||||
mux2 #(1) numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
|
||||
mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
|
||||
// CT *** fdivsqrtfplead1
|
||||
|
||||
//////////////////////////////////////////////////////
|
||||
// Floating-Point Preprocessing
|
||||
// append leading 1 (for nonzero inputs)
|
||||
// shift square root to be in range [1/4, 1)
|
||||
// Normalized numbers are shifted right by 1 if the exponent is odd
|
||||
// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
|
||||
//////////////////////////////////////////////////////
|
||||
|
||||
assign DivX = {3'b000, ~NumerZeroE, Xfract};
|
||||
|
||||
// Sqrt is initialized on step one as R(X-1), so depends on Radix
|
||||
mux2 #(P.DIVb+1) sqrtxmux({~XZeroE, Xfract}, {1'b0, ~XZeroE, Xfract[P.DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
|
||||
if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
|
||||
else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
|
||||
mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
|
||||
|
||||
//////////////////////////////////////////////////////
|
||||
// Selet integer or floating-point operands
|
||||
//////////////////////////////////////////////////////
|
||||
|
||||
if (P.IDIV_ON_FPU) begin
|
||||
mux2 #(P.DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
|
||||
end else begin
|
||||
assign X = PreShiftX;
|
||||
end
|
||||
|
||||
// Divisior register
|
||||
flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {4'b0001, Dfract}, D);
|
||||
|
||||
// Floating-point exponent
|
||||
fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
|
||||
flopen #(P.NE+2) expreg(clk, IFDivStartE, QeE, QeM);
|
||||
|
||||
// Number of FSM cycles (to FSM)
|
||||
fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .CyclesE);
|
||||
|
||||
if (P.IDIV_ON_FPU) begin:intpipelineregs
|
||||
// pipeline registers
|
||||
flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM);
|
||||
flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM);
|
||||
flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
|
||||
flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
|
||||
flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
|
||||
flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
|
||||
flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
|
||||
flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
|
||||
flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
|
||||
if (`XLEN==64)
|
||||
flopen #(P.DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
|
||||
flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
|
||||
flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);
|
||||
if (P.XLEN==64)
|
||||
flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
|
||||
end else begin
|
||||
assign NumerZeroE = XZeroE;
|
||||
assign X = PreShiftX;
|
||||
end
|
||||
|
||||
// Sqrt is initialized on step one as R(X-1), so depends on Radix
|
||||
if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
|
||||
else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
|
||||
mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
|
||||
|
||||
// Floating-point exponent
|
||||
fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
|
||||
flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
|
||||
|
||||
// Number of FSM cycles (to FSM)
|
||||
fdivsqrtcycles cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .cycles);
|
||||
endmodule
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user