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1777 Commits

Author SHA1 Message Date
Skylar Litz
99a15e7897 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
Kevin Kim
a7684f1b59 Makefile added in regression directory: 
-cd's into imperas then runs make commands, finally running the tvLinker script
 2021-11-09 10:55:48 -08:00
bbracker
1597e0dac6 increase expectations for buildroot and timeout count 2021-11-06 14:57:29 -07:00
bbracker
24d3244cfe checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
bbracker
e4cf044932 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
bbracker
8563c0f016 linux testgen refactor 2021-11-01 14:09:49 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
bbracker
38d26e857b fix buildroot graphical sim 2021-10-31 18:33:43 -07:00
David Harris
e9244e7a85 Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
f35b31f166 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-29 22:32:08 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb rearranging testgen 2021-10-29 22:28:37 -07:00
Ross Thompson
8aad95366d Fixed the 4 way set associative pseudo LRU replacement policy. 2021-10-29 12:46:02 -05:00
Ross Thompson
f61fcd25a9 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. 2021-10-29 11:03:37 -05:00
Ross Thompson
54c714d222 Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. 2021-10-28 11:07:18 -05:00
bbracker
fe2bf13720 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 14:40:31 -07:00
bbracker
d14fa074ec checkpoint generator off-by-one error fix 2021-10-27 14:10:29 -07:00
Noah Limpert
21ea270fe2 Have replaced .* with signal names in ifu 2021-10-27 13:45:37 -07:00
koooo142857
0a33b0904d aligned all files in ifu folder 2021-10-27 12:43:55 -07:00
David Harris
e62b57e2c2 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
9cfb8deaab Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
David Harris
31a2346c37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-27 10:37:46 -07:00
David Harris
0421b7af56 Changes for floating point sims 2021-10-27 10:37:35 -07:00
Ross Thompson
fed8882aec Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-27 09:59:55 -05:00
Ross Thompson
d98baf90a3 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
Ross Thompson
0817ef20f1 Linux now boots fpga. 2021-10-26 16:49:16 -05:00
bbracker
52529db40b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-26 12:43:48 -07:00
bbracker
1409dc48a8 bugfix argument passing to GDB script; remove outdated GDB script 2021-10-26 12:43:42 -07:00
David Harris
f793dd7a5e removed unused signal from wave.do 2021-10-26 09:02:22 -07:00
David Harris
7d516c65e7 commented out nonworking tests 2021-10-26 08:56:49 -07:00
David Harris
ca700610f8 removed referenc outputs 2021-10-26 08:51:49 -07:00
David Harris
1a6fb2fad9 Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
79c1395967 merging changes 2021-10-26 08:34:36 -07:00
David Harris
44de52a05a Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
09b3549efd Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
cb7015a690 Fixed the timing issue in the cache replacement polcy. 2021-10-25 18:00:23 -05:00
Ross Thompson
6c92d3267f Fixed bug with the changes to sram1rw. 2021-10-25 16:11:41 -05:00
Ross Thompson
c963ea1a64 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-25 15:36:21 -05:00
Ross Thompson
694b3fbb6f Possible fix for critical path timing in caches. 2021-10-25 15:33:33 -05:00
bbracker
f39a509b5b adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
f50787203f copy / link to checkpoint 8500000 dir 2021-10-25 13:24:02 -07:00
Ross Thompson
2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
c61cbf9618 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
Ross Thompson
f7583d0e0d Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
14e6d2c576 Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
b51e4d504b some linux testbench cleanup 2021-10-25 10:04:30 -07:00
Ross Thompson
ebef47b1c9 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
d348ebffda checkpoint initialization bugfix 2021-10-24 18:39:51 -07:00
bbracker
9423b90780 switch linux graphical sim over to Ross's waves 2021-10-24 18:39:23 -07:00
bbracker
9cdbd9a0bf remove unused scripts 2021-10-24 15:19:03 -07:00
bbracker
4100ed9a7a update debugger script to new style 2021-10-24 15:18:44 -07:00
bbracker
3c118437de fix typo 2021-10-24 15:05:00 -07:00
bbracker
eb9740bc31 manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
0a32d79370 checkpoint generator bugfix 2021-10-24 14:46:56 -07:00
Ross Thompson
87aaec3b6c Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
4544d28bc9 or actually needed to reduce expectations of buildroot 2021-10-24 06:59:34 -07:00
bbracker
23bff55c6e increase regression's expectations of buildroot 2021-10-24 06:50:22 -07:00
bbracker
dcd4d9dd9f add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
35ccab0e29 revamp linux testvector generation for refactoring checkpoint generation 2021-10-24 06:14:11 -07:00
bbracker
366cb12a13 buildroot do scripts now compile flops 2021-10-23 23:14:59 -07:00
bbracker
f6911be937 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
3b63dde570 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
d6fb441666 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
67f3fc9962 wrapping up lint cleanup; many unused signals removed 2021-10-23 12:15:14 -07:00
David Harris
106982e493 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34 more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
b6bb33ecef lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
5e961973cb IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
708b914a65 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
817795f619 Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
2abec36221 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2 FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
kipmacsaigoren
c2f4b49b15 removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
James E. Stine
a60e19dc3f Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00