David Harris
cc06fa1c55
Cleaned bram interface
2022-06-08 01:39:44 +00:00
David Harris
f81719337e
Added ahbapbbridge and cleaning RAM
2022-06-08 01:31:34 +00:00
Katherine Parry
74b549ddc8
paramerterized some small fma units
2022-06-01 23:34:29 +00:00
Katherine Parry
559c0c278e
added unpackinput.sv
2022-05-31 16:18:50 +00:00
Katherine Parry
3c63db9554
some optimizations in unpacker
2022-05-27 11:36:04 -07:00
Katherine Parry
b288f812ab
moved lzc to generic and small optimizations on fcvt
2022-05-27 09:04:02 -07:00
Ross Thompson
0ed34b8e63
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-04 10:56:10 -05:00
Ross Thompson
0806d1a134
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
2022-04-04 10:38:37 -05:00
Ross Thompson
f58a1eff9e
Fixed linting issues.
2022-04-01 15:20:45 -05:00
Ross Thompson
fb0eec0f76
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-31 11:39:41 -05:00
Ross Thompson
0942429b7f
Forced to go back to hard coded preload.
2022-03-31 11:39:37 -05:00
Ross Thompson
dc48d84dd6
Modified clint to support all byte write sizes.
2022-03-31 11:31:52 -05:00
Ross Thompson
370a075fa1
Partial cleanup of memories.
2022-03-30 11:09:21 -05:00
Ross Thompson
1993069986
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
2022-03-30 11:04:15 -05:00
Ross Thompson
de2672231d
Partial fix to allow byte write enables with fpga and still get a preload to work.
2022-03-29 19:12:29 -05:00
Ross Thompson
bdfca503fa
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
50789f9ddd
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
David Harris
3e16730226
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
8bf73d0eb3
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
Ross Thompson
4ecc2d029a
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
a5a89e58a8
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
d66f7c841b
Removed generate statements
2022-01-05 14:35:25 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
