Ross Thompson 5726b5b640 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.		2022-01-13 22:21:43 -06:00
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flop	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
adder.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
arrs.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
clockgater.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
counter.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
decoder.sv	Fixed unpacking bug; regression runs again	2022-01-06 18:22:30 +00:00
mux.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
neg.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
onehotdecoder.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
or_rows.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
priorityonehot.sv	Fixed unpacking bug; regression runs again	2022-01-06 18:22:30 +00:00
prioritythermometer.sv	Fixed unpacking bug; regression runs again	2022-01-06 18:22:30 +00:00