Ross Thompson
c90d129498
Fixed boot loader program to start at correct address.
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modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
2021-10-11 17:22:23 -05:00
Ross Thompson
cbf4e76d1c
Fixed sdc byte and nibble orders.
2021-10-11 12:15:52 -05:00
Ross Thompson
2e0dcaaff9
Fpga simualtion files.
2021-10-11 10:24:40 -05:00
Ross Thompson
3d9d4cc03f
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
Ross Thompson
e4e353c186
updated fpga wavefile.
2021-10-03 12:14:22 -05:00
Ross Thompson
4c81d3453e
Added fpga wave file.
2021-10-03 11:56:11 -05:00
Ross Thompson
c10261f0ad
Added more debug flags.
2021-10-03 11:41:21 -05:00
Ross Thompson
ec4a07de64
Movied tristate to test bench level.
2021-09-30 11:27:42 -05:00
Ross Thompson
db18aac9af
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
Ross Thompson
99070127d8
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
Ross Thompson
f2c1ca4bd5
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
6ac96db20b
Merge branch 'main' into fpga
2021-09-26 13:22:53 -05:00
Ross Thompson
6dc25e07c2
Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
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the flash card to dram.
Fixed latch issue in the sd card reader.
2021-09-26 13:22:23 -05:00
Ross Thompson
55f3c15302
Merge branch 'sdc' into fpga
2021-09-25 19:33:07 -05:00
Ross Thompson
8e29d4472e
GPIO marker to indicate the sdc to dram transfer complete.
2021-09-25 19:29:15 -05:00
Ross Thompson
5bdd6a9d0c
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
3a15cc7872
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
43d386f9f3
Updated ignore file.
2021-09-24 18:48:45 -05:00
Ross Thompson
dd9fe60b28
Write of the SDC address register is correct. The command register is not yet working.
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The root problem is the command register needs to be reset at the end of the SDC transaction.
2021-09-24 18:48:11 -05:00
Ross Thompson
5663522a3f
Now have software interacting with the initialization and settting the address register.
2021-09-24 18:30:26 -05:00
Ross Thompson
232d4a554f
Have program which checks for sdc init and issues read, but read done is
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not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Kip Macsai-Goren
077f125c13
updated pmp outputs with new exectuaion tests
2021-09-24 16:30:16 -04:00
Kip Macsai-Goren
cd5b4034e5
updated execute tests, light cleanup, privilege mode changes still need fix.
2021-09-24 16:29:56 -04:00
Kip Macsai-Goren
603667e1e6
updated test library to include: simpler execution tests, widths for each read/write, outputs for pmpaddr writes.
2021-09-24 16:28:53 -04:00
Kip Macsai-Goren
bb0bc816c5
completed and cleaned up pmp tests, including execute tests
2021-09-24 16:18:44 -04:00
Ross Thompson
71e20c7f61
Fixed lint errors in the SDC.
2021-09-24 12:38:48 -05:00
Ross Thompson
0f87f68b9d
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
Ross Thompson
af28cfb70c
Added SDC defines to each config mode.
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Added sd_top which is the sd card reader.
2021-09-24 12:24:30 -05:00
Ross Thompson
0a33f5fa46
setup so the sdc does not need to load a model in the imperas test bench.
2021-09-24 11:30:52 -05:00
Ross Thompson
78028947bf
Updated Imperas test bench to work with the SDC reader.
2021-09-24 11:22:54 -05:00
Ross Thompson
4256ef82b1
SDC to ABHLite interface partially done.
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Added SDC to adrdec and uncore.
2021-09-24 10:45:09 -05:00
Ross Thompson
a182263b1c
Added clock gater and divider to generate the SDCCLK.
2021-09-23 17:58:50 -05:00
Ross Thompson
9ed7a1f494
Partial implementation of SDC AHBLite interface.
2021-09-23 17:45:45 -05:00
Ross Thompson
0f7be5e591
Started the AHBLite to SDC interface.
2021-09-22 18:08:38 -05:00
bbracker
441759b81c
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
b1c2a77fc2
update setup scripts to new testvector files
2021-09-22 12:31:10 -04:00
Ross Thompson
d4f514010d
Changes to make fpga synthesizable.
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Added preload to test simple program on wally in fpga.
2021-09-22 10:54:13 -05:00
Ross Thompson
f5905f33d3
Initial SD Card reader.
2021-09-22 10:50:29 -05:00
Ross Thompson
d09b381183
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
8fa287a449
The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0
Added counters to walk through d cache flush.
2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d
Added flush controls to cachway.
2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
bbracker
92ddc9b20a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-15 17:31:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
bbracker
f94a13e242
created script to determine which functions are most frequently used
2021-09-14 19:41:05 -04:00
