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Configurable RISC-V Processor
1,694 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Ross Thompson 232d4a554f Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP Have program which checks for sdc init and issues read, but read done is 2021-09-24 15:53:38 -05:00
wally-pipelined Have program which checks for sdc init and issues read, but read done is 2021-09-24 15:53:38 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor