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Configurable RISC-V Processor
1,722 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
4c81d3453e
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Ross Thompson 4c81d3453e Added fpga wave file.
2021-10-03 11:56:11 -05:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP added support to due partial fpga simulation. 2021-09-26 15:00:00 -05:00
wally-pipelined Added fpga wave file. 2021-10-03 11:56:11 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore Updated ignore file. 2021-09-24 18:48:45 -05:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor