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234 Commits

Author SHA1 Message Date
Katherine Parry
19116ed889 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Kip Macsai-Goren
a84dd6dfc5 added tests for SV48 and translation off with vmem 2021-06-03 14:28:52 -04:00
James E. Stine
bccdd2c137 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
8f9680556f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
5bc2a8b346 Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
927aec34a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Katherine Parry
0646e08609 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
bd05de0dbb FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
Kip Macsai-Goren
ba134eb166 partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields 2021-05-24 20:59:26 -04:00
James E. Stine
1704fdc877 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
Ross Thompson
3c5e87d6c2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
daf344f1ba Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
bbracker
142b02b30a improved PLIC test organization 2021-05-21 15:13:02 -04:00
James E. Stine
49a4097d97 Minor testbench updates to rv64icfd 2021-05-21 09:41:21 -05:00
James E. Stine
47487a625f Update to testbench-imperase for rv64icfd 2021-05-21 09:28:44 -05:00
James E. Stine
694e21541b Update to FLD/FSD testbench 2021-05-21 09:26:55 -05:00
James E. Stine
474d479280 Update to rv64icfd wally-config to run through FP tests 2021-05-21 09:22:17 -05:00
Katherine Parry
67a41748ba FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
fd4fae0406 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
f407bee5ae Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
David Harris
7dcc53dcf5 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
James E. Stine
41da78e0b6 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
Domenico Ottolia
1c884338b0 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
ushakya22
6274c8cb80 Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Domenico Ottolia
14becde792 Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
ushakya22
da352c81e7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
66344f0604 Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Domenico Ottolia
2c39c0a6a5 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
7c2481bea6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
4db3780ebb Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
39135f221e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
1556cc5b9f Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
Domenico Ottolia
84911e6345 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
12d8ff617b Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238 Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9 finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7 updated pipeline tests 2021-05-03 22:07:36 -04:00
David Harris
699a8f3ac3 Extended maximum signature length to 1M 2021-05-03 15:29:20 -04:00
bbracker
acd99be7f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 09:23:52 -04:00
Katherine Parry
9252d08b41 fpu imperas tests run 2021-05-01 02:18:01 +00:00
bbracker
0d62440f60 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359 rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Domenico Ottolia
830787e3e1 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Domenico Ottolia
750d276feb Minor improvements to scause test 2021-04-29 16:48:07 -04:00
Domenico Ottolia
fdbd238a87 Add machine-mode timer interrupts to mcause tests 2021-04-29 16:39:18 -04:00
Domenico Ottolia
c9cb2f51d1 Same but don't break sim-wally this time 2021-04-29 15:33:27 -04:00
Domenico Ottolia
fdd4deec2f Add more exceptions to medeleg tests 2021-04-29 15:32:13 -04:00
ushakya22
f139f248dc Working MIE timer tests 2021-04-29 15:19:43 -04:00
Domenico Ottolia
99a927be47 Add medeleg tests 2021-04-29 15:02:36 -04:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Ross Thompson
44d28dbd1c Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
Shriya Nadgauda
2a5c243b0b adding pipeline testing 2021-04-23 14:19:17 -04:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Thomas Fleming
f9e071baf8 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
Domenico Ottolia
82320033d5 Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00