David Harris
c17b0c7d45
Improved naming of signals in TLB
2024-12-24 05:36:20 -08:00
Zain2050
7d57d83224
made changes for ResEnc in tlbcontrol
2024-12-24 01:38:03 -08:00
David Harris
45d4bf0f60
Typo fix
2024-12-23 06:22:11 -08:00
Rose Thompson
5011084d40
Revert "This is a better solution. It's closer to the original book HPTW FSM,"
...
This actually adds to the critical path and it's more complex than I feel comfortable.
This reverts commit 1ded4a972f
2024-10-11 17:02:51 -05:00
Rose Thompson
1ded4a972f
This is a better solution. It's closer to the original book HPTW FSM,
...
but is slightly more complex in RTL. Instead it looks at ReadDataM
for the PTE for PBMT faults. I was worried this would cause critical
path issues but I think it is ok. ReadDataM is used only to created
PBMT and this directly controlls the enable to a flop and the state
inputs to the FSM.
2024-10-11 16:47:18 -05:00
Rose Thompson
4c7eb1d11f
Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW.
2024-10-11 15:41:40 -05:00
Rose Thompson
37d3db916b
Resolved the HPTW's not taking the PBMT fault on the right cycle by
...
having the fsm branch to fault on any cycle a HPTWFaultM occurs. This
of course changes the figure in the book but it really relevant to
PBMT. This appeared to work because the HPTW happened to also generate
an access fault at the end of the walk and the logic produced both
faults. I wrote new test which confirms just the one is generated.
2024-10-11 15:31:20 -05:00
Rose Thompson
7a92d41ef5
Simplified logic around IgnoreRequest and HPTWFaultM.
2024-10-11 14:41:52 -05:00
Rose Thompson
fe5f342d2f
Does not work. But there is a bug hiding the IgnoreRequest confusion.
2024-10-11 12:07:26 -05:00
Rose Thompson
6a905aa2f2
Possible start to resolution on issue #839 .
2024-10-10 17:14:27 -05:00
Rose Thompson
35693eb7cc
Fixed bug so AMO access faults only produce StoreAmoAccessFault and
...
not both LoadAccessFault adn StoreAmoAccessFault.
2024-10-02 14:04:01 -05:00
Rose Thompson
2112c705a4
Supress misaligned faults during a tlb miss. Still needs to be tested.
2024-09-30 15:55:46 -05:00
David Harris
ffb248dc65
Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit
2024-07-05 21:32:57 -07:00
David Harris
0ab3f28991
Lint cleanup
2024-06-20 00:10:03 -07:00
Ross Thompson
91c844ca45
Removed more *** from camline and csrc.
2024-06-19 12:31:50 -07:00
Ross Thompson
9b6b6617af
Cleaned up hptw.
2024-06-19 12:02:56 -07:00
Ross Thompson
24916d42e2
Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw.
2024-06-19 11:40:02 -07:00
Ross Thompson
71f267a17a
Added InstrUpdateDAF to the HPTW.
2024-06-19 11:09:49 -07:00
David Harris
cb563e8018
Clean up unused signals
2024-06-18 08:07:14 -07:00
David Harris
c1fd7a9589
Removed unused signals
2024-06-18 07:28:52 -07:00
David Harris
8bae52b09d
Lint cleanup of unused signals
2024-06-18 06:49:17 -07:00
David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
David Harris
3f195884e9
Defined bit sizes more precisely to help VCS lint and conform to coding style
2024-04-21 08:40:11 -07:00
David Harris
b386331cc8
Changed '0 to 0 where possible per Chapter 4 style guidelines
2024-03-06 05:48:17 -08:00
David Harris
86956026dc
Further simplified subwordread muxing
2024-03-06 04:24:31 -08:00
David Harris
90e89ced1d
Fixes for synthesis. HPTW change will break x detection
2024-02-26 04:20:08 -08:00
harshinisrinath
c7b647bde7
Wrote exclusions for ifu and lsu peripherals which were always supported
2024-02-01 17:12:33 -08:00
David Harris
45e2317636
Added Wally github address to header comments
2024-01-29 05:38:11 -08:00
David Harris
1c1d3eb956
HPTW coverage improvements
2024-01-26 10:46:38 -08:00
David Harris
2449e06e55
Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported
2024-01-25 21:03:41 -08:00
David Harris
171430a695
FPU and PMP tests
2024-01-21 14:41:22 -08:00
David Harris
911b400af2
Fault on misaligned AMO
2024-01-18 13:13:56 -08:00
Rose Thompson
e8474373e4
Fixed it so Virtual Memory work without a D$.
2024-01-18 09:18:17 -06:00
David Harris
67124b0c7f
Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough
2024-01-06 07:11:25 -08:00
David Harris
0781cd4a44
Improved tlbcontrol to fault on R=0,W=1; fixed more coverage testsin tlbmisc.S; changed integer type to try to speed up CoreMark; comments in Verilate
2024-01-05 22:45:15 -08:00
Rose Thompson
1f3792c823
Fixed bug # 547, but there are other bugs which follow.
2024-01-05 23:32:10 -06:00
Rose Thompson
edc56c669e
Fixed bug 546. non-leaf non-zero PBMT bit raise page fault.
2024-01-05 17:10:14 -06:00
David Harris
680a014876
Finished LSU tlbcontrol coverage tests
2024-01-02 10:16:20 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
David Harris
c52aef86a6
Fixed coverage exclusions that no longer reference code properly
2023-12-31 20:35:08 -08:00
David Harris
536539237c
Fixed exclusion tags in pmachecker
2023-12-31 20:20:31 -08:00
David Harris
e8df856fdb
Renamed CMOp to CMOpM in mmu and cache
2023-12-25 05:57:41 -08:00
David Harris
6395cd0284
Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match
2023-12-21 12:29:37 -08:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
18a96740d5
Revert RAM logic to bit change.
...
Added logic to hptw to prevent x propagation.
2023-12-20 13:10:20 -06:00
David Harris
166c98b6f6
Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn
2023-12-13 19:43:17 -08:00
David Harris
333e390f8d
Test commit from dev
2023-12-13 11:52:21 -08:00
David Harris
6c017141c5
Renamed HADE to ADUE for Svadu
2023-12-13 11:49:04 -08:00
