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Typo fix

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David Harris 2024-12-23 06:22:11 -08:00
parent 19495af18a
commit 45d4bf0f60
1 changed files with 1 additions and 1 deletions
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src/mmu/tlb/tlbram.sv
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@ -51,6 +51,6 @@ module tlbram import cvw::*; #(parameter cvw_t P,
or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
// Rename the bits read from the TLB RAM
assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bitss
assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits
assign PPN = PageTableEntry[P.PPN_BITS+9:10];
endmodule