Rose Thompson
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c061440141
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First stab at the misaligned test.
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2023-10-31 12:30:10 -05:00 |
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David Harris
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dccd7bf5ee
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Fixes to config extraction
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2023-10-31 06:27:55 -07:00 |
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David Harris
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5112bfed19
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130 nm synthesis script improvements
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2023-10-30 20:57:35 -07:00 |
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David Harris
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680fb3f30b
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Conditionally instantiate hardware in ifu
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2023-10-30 20:55:00 -07:00 |
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David Harris
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afabc52b61
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Gated InstrOrigM and PCMReg when not needed
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2023-10-30 20:05:37 -07:00 |
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David Harris
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2d17a991d8
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rom1p1r code cleanup
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2023-10-30 19:47:49 -07:00 |
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David Harris
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3f7c67882f
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rom1p1r code cleanup
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2023-10-30 19:46:38 -07:00 |
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David Harris
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90a178e31e
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Made 2-bit AdrReg conditional on being needed
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2023-10-30 19:13:43 -07:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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2241976d29
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Updated mmu to not generate trap on cacheable misaligned access when supported.
Updated tests with David's help.
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2023-10-30 18:26:11 -05:00 |
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Rose Thompson
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f13b67b869
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Preemptively fixed the bytemask bug before testing.
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2023-10-30 15:47:46 -05:00 |
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Rose Thompson
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b5763e11e8
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rv32gc now also works with the alignment module. Still not tested with misligned access.
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2023-10-30 15:30:09 -05:00 |
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Rose Thompson
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9cd2e47783
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Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.
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2023-10-30 14:54:58 -05:00 |
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Rose Thompson
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569e3dc906
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Finally lints cleanly.
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2023-10-30 14:00:49 -05:00 |
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Rose Thompson
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89de8cd23c
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Merge pull request #445 from davidharrishmc/dev
Fix issue 444; no delegating misaligned instructions if they can't happen
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2023-10-30 12:25:42 -05:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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David Harris
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27b8ebb9bd
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Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported.
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2023-10-30 07:06:34 -07:00 |
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Rose Thompson
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dce3c85105
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Progress.
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2023-10-27 16:31:22 -05:00 |
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Rose Thompson
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747f453bb5
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Passes lint with some exceptions. Still need to add misaligned store support.
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2023-10-27 14:41:42 -05:00 |
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Rose Thompson
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36ca64c567
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At least have the aligner integrated, but not tested.
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2023-10-27 13:55:16 -05:00 |
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Rose Thompson
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657409aec5
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Addec ZICCLSM to config files and started on lsu instance.
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2023-10-27 13:07:23 -05:00 |
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Rose Thompson
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6041bf20b3
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The misaligned load alignment lints.
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2023-10-27 11:41:49 -05:00 |
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Rose Thompson
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834c0df697
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Added file.
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2023-10-27 09:49:44 -05:00 |
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Rose Thompson
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449abef823
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Progress on misaligned load/stores.
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2023-10-27 09:35:44 -05:00 |
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Rose Thompson
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50a1d731c0
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Merge pull request #443 from davidharrishmc/dev
Wrapper synthesis fix.
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2023-10-27 09:25:06 -05:00 |
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David Harris
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09c4aaa5d9
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Fixed reporting of timing on modules with wrappers
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2023-10-26 20:14:14 -07:00 |
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David Harris
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734bf021d7
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-10-26 19:02:05 -07:00 |
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David Harris
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8cf81a2bb8
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Merge pull request #441 from ross144/main
Fixed issues #200
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2023-10-26 10:26:58 -07:00 |
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Rose Thompson
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06b5a92eff
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Updated comments about Interrupt and wfi.
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2023-10-26 12:24:36 -05:00 |
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Rose Thompson
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4cd0584a11
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Forgot to include this file in the last commit.
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2023-10-26 12:20:42 -05:00 |
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Rose Thompson
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14f8b4849f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-26 12:15:22 -05:00 |
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Rose Thompson
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12763b7297
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begin implemenation of Zicclsm.
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2023-10-26 11:51:20 -05:00 |
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Rose Thompson
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3322ff915e
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Cleaned up the implementation changes for wfi.
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2023-10-24 23:11:48 -05:00 |
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Rose Thompson
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c58f04c901
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This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps.
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2023-10-24 22:58:26 -05:00 |
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Rose Thompson
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c61526d034
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Possible fix for wfi.
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2023-10-24 18:08:33 -05:00 |
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David Harris
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3bb7539429
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Fixed warnings of signed conversion and for Design Compiler
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2023-10-24 14:01:43 -07:00 |
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David Harris
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905c5da7a9
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Tested assembly language file for the pause example
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2023-10-24 10:45:41 -07:00 |
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David Harris
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ea571a6e3b
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Merge pull request #439 from ross144/main
Fixes to branch predictor processing scripts.
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2023-10-24 08:31:06 -07:00 |
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Rose Thompson
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bd04ffc0c9
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Fixed bug in bpred-sim.py for btb and class size sweep.
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2023-10-24 10:29:02 -05:00 |
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Rose Thompson
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4fe58fe036
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-23 16:14:30 -05:00 |
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Rose Thompson
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ea403e02ff
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Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction.
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2023-10-23 16:09:40 -05:00 |
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Rose Thompson
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694ec18934
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Added support for branch counters when there is no branch predictor.
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2023-10-23 15:32:03 -05:00 |
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Rose Thompson
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1611d5ec3c
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Fixed issue 250. instruction classification was not correct for jalr ra (non zero).
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2023-10-23 15:30:43 -05:00 |
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Rose Thompson
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2aecf688f9
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Addeed script to sweep sim_bp for btb.
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2023-10-23 15:29:50 -05:00 |
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David Harris
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eba346849c
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Merge pull request #438 from ross144/main
Fixed comments in cboz and cbom tests.
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2023-10-20 17:15:59 -07:00 |
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Rose Thompson
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0fd5b3b2ce
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Updated comments in the cboz tests.
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2023-10-20 15:15:47 -05:00 |
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Rose Thompson
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0aea2c80b8
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-10-20 15:14:02 -05:00 |
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Rose Thompson
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5a4028064a
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Updated comments for the cbom tests.
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2023-10-20 15:13:52 -05:00 |
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Rose Thompson
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d6dcec458d
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Merge pull request #437 from davidharrishmc/dev
synth improvements
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2023-10-19 16:23:34 -05:00 |
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