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131 Commits

Author SHA1 Message Date
David Harris
8552369687 Merged PR538, delete unused tests 2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019 All regression tests which matter are running! 2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59 Updated tests with ending label. 2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89 Reverted logic to bit change. 2023-12-20 13:16:32 -06:00
Rose Thompson
a8ab3c8342 Ok that is a stange bug. 
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
 2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe Almost working with modelsim and verilator. 2023-12-20 11:29:31 -06:00
David Harris
5dbca251d8 Defined new Zicboz and Zcb tests 2023-12-19 13:24:11 -08:00
Rose Thompson
2e792606dd More progress. Most tests are passing in modelsim. 2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3 Progress. 2023-12-18 20:23:19 -06:00
Rose Thompson
1e1759c258 Restored the one hack change which prevents verilator from working. 2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
Rose Thompson
c1ac153a4f Closer to verilator support. 2023-12-18 16:26:56 -06:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
David Harris
38f4d9baf8 Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e 2023-12-15 05:05:53 -08:00
David Harris
68d96a929c Fixed hierarchical path to EcallFaultM in testbench 2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8 Rolled back attempt to support Verilator 2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
Jacob Pease
a1e7158bd9 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
Rose Thompson
38b327eaf8 Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters. 2023-11-17 11:21:25 -06:00
Jacob Pease
23e5fca2a7 Merge branch 'main' of github.com:jacobpease/cvw 2023-11-16 14:04:11 -06:00
Rose Thompson
da59cb71a9 Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config. 2023-11-13 14:12:27 -06:00
David Harris
4de21c206f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-03 16:04:10 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
naichewa
a08356fdaa correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Jacob Pease
3e891ee635 Merge branch 'main' of github.com:openhwgroup/cvw 2023-10-17 14:13:28 -05:00
Jacob Pease
2b1c604016 Slight modification to testbench.sv 2023-10-17 14:13:18 -05:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
c1d6fddea8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
9a49ec0b98 Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
7f79c0a855 Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
Ross Thompson
4d76e83318 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
8f09e17dc7 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
6330e8084c more testbench improvements. 2023-06-14 12:23:26 -05:00