David Harris
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ca1f7ce5d3
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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David Harris
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0d0aa59e48
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Removed imperas tests from makefile for now
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2022-01-20 14:51:56 +00:00 |
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David Harris
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f420e63ed0
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Added top-level make clean
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2022-01-20 14:17:26 +00:00 |
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David Harris
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537cb1d1e1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-20 00:04:27 +00:00 |
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David Harris
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f966d98e56
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-19 00:26:34 +00:00 |
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Ross Thompson
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5cf686429d
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Merged in the debug ila updates.
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2022-01-18 17:29:21 -06:00 |
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Ross Thompson
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2508b9d35a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-18 17:19:59 -06:00 |
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Ross Thompson
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fdc17f5017
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Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
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2022-01-18 17:19:33 -06:00 |
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David Harris
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1a21e7f011
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riscvsingle reparittioned to match Ch4
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2022-01-17 16:57:32 +00:00 |
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David Harris
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de7b9c127e
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Added E extension, and downloaded riscv-dv and embench-iot to addins
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2022-01-17 14:42:59 +00:00 |
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David Harris
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5842d780a7
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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David Harris
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8b62130070
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lsu cleanup down to 346 lines
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2022-01-15 01:19:44 +00:00 |
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David Harris
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b967bcede2
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LSU Cleanup
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2022-01-15 01:11:17 +00:00 |
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David Harris
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f7f3882cb8
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Moved Dcache into bus block
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2022-01-15 00:39:07 +00:00 |
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David Harris
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d9e8d16bbe
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Renamed LSUStall to LSUStallM
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2022-01-15 00:24:16 +00:00 |
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David Harris
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b0263012e8
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LSU cleanup
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2022-01-15 00:11:30 +00:00 |
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David Harris
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4c5962095e
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LSU cleanup
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2022-01-15 00:03:03 +00:00 |
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David Harris
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37bf5347cf
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LSU cleanup
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2022-01-14 23:55:27 +00:00 |
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Ross Thompson
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dd1ebb75f0
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Fixed spillthreshold warning.
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2022-01-14 17:23:39 -06:00 |
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Ross Thompson
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9d2a79f180
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-14 17:16:53 -06:00 |
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David Harris
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380e990def
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moved fp to tests
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2022-01-14 23:05:59 +00:00 |
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David Harris
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291deb5c39
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LSU partitioning
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2022-01-14 23:02:28 +00:00 |
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David Harris
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36d49a8a74
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Moved fp tests from testbench to tests/fp
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2022-01-14 23:00:46 +00:00 |
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Ross Thompson
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db519a0dca
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Cleanup IFU comments.
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2022-01-14 15:06:30 -06:00 |
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Ross Thompson
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a70e12ad75
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Optimization in the ifu. Please note this optimization is not strictly correct,
but is possible. See comments in the ifu source code for details.
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2022-01-14 12:16:48 -06:00 |
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Ross Thompson
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a549079672
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More ifu cleanup.
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2022-01-14 11:19:12 -06:00 |
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Ross Thompson
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ce937a35a8
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Added tim only test to regression-wally. Minor cleanup to ifu.
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2022-01-14 11:13:06 -06:00 |
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James E. Stine
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115ea7dbb0
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Update to TestFloat for scripts so can run automatically once
TestFloat/Softfloat is compiled. Slight change to the README as well.
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2022-01-14 09:25:37 -06:00 |
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Ross Thompson
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5726b5b640
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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Ross Thompson
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9f7e3f147b
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Partial local dtim in lsu configuration.
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2022-01-13 17:50:31 -06:00 |
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David Harris
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d356a0d29f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-13 21:46:00 +00:00 |
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David Harris
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e3f6c398b5
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Mixed C and assembly language test cases; SRT initial version passing tests
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2022-01-13 21:45:54 +00:00 |
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Ross Thompson
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0b06fa12ef
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Merge branch 'testDivInterruptInterlock' into main
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2022-01-13 11:21:48 -06:00 |
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Ross Thompson
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93cb24476f
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Fixed interger divide so it can be interrupted.
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2022-01-13 11:16:50 -06:00 |
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Ross Thompson
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4bcabd1a55
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Removed unused inputs to hptw.
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2022-01-13 11:04:48 -06:00 |
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Ross Thompson
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654a33bf92
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Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
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2022-01-12 17:41:39 -06:00 |
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Ross Thompson
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861450c4d6
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Fixed support to allow spills and no icache.
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2022-01-12 17:25:16 -06:00 |
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Ross Thompson
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000d713cb5
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Better solution to the integer divider interrupt interaction.
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2022-01-12 14:22:18 -06:00 |
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Ross Thompson
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26fb09c868
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Added additional fsm to ILA.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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6eb2f37ce4
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Possible fix for the TrapM DTLBMiss suppression.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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6b483e621d
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If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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48c036a923
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Oups. My hack for DivE interrupt prevention was wrong.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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796316495d
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Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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ecd3912900
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Set rv32ic to not use icache.
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2022-01-12 14:10:09 -06:00 |
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Ross Thompson
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2ed052f152
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-12 13:29:19 -06:00 |
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Ross Thompson
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87485f9f64
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Improve wavefile by adding performance counters.
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2022-01-12 10:53:29 -06:00 |
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Kip Macsai-Goren
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c99456d5e7
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Fixed PMA regions, Added passing PMA tests to regression
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2022-01-10 22:08:26 +00:00 |
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David Harris
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4cae11ad28
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Merged coremark changes
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2022-01-10 05:09:28 +00:00 |
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David Harris
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50c17f2a03
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Removed unused coremark_bare
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2022-01-10 05:05:55 +00:00 |
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David Harris
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467aac8463
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Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
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2022-01-10 05:04:13 +00:00 |
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