David Harris
aa0d0d50d8
Added fp test to testbench
2021-03-26 13:03:23 -04:00
Teo Ene
1e691e120b
Fix typo from last commit
2021-03-24 17:09:58 -05:00
Teo Ene
6a7b69ff2d
Updated coremark_bare testbench for IM
2021-03-24 17:04:43 -05:00
Domenico Ottolia
3909158619
re-organize privileged tests to be in rv64p to rv32p folders
2021-03-24 13:51:25 -04:00
Noah Boorstin
43d23e3d9b
busybear: add better warning on illegal instruction
...
...also it seems that mret is being picked up as an illegal instruction??
2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0
busybear: temporarially force rf[5] correct after failure to read CSR
2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0
busybear: finally get the right error
2021-03-22 16:52:22 -04:00
Noah Boorstin
7350b9f18f
busybear: comment out some debug printing
2021-03-22 14:54:05 -04:00
Noah Boorstin
c4fb51fad1
regression: expect 200k instead of 100k busybear instrs
...
and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
Shreya Sanghai
804407eab7
fixed minor bugs in testbench
2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Teo Ene
0ff785549e
Switched coremark to RV64IM
2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed
adapted coremark bare testbench to new dtim RAM HDL
2021-03-17 16:59:02 -05:00
Teo Ene
29634f1475
Temporarily reverted my last few commits
2021-03-17 15:16:01 -05:00
Teo Ene
90946d61c5
fix to last commit
2021-03-17 15:02:15 -05:00
Teo Ene
ca901513c8
Added Ross's addr lab stuff to coremark stuff
2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778
fixing coremark branch prediction
2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
a3b2ffb2c9
Merge branch '3_3_2021' into main
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Making sure coremark works with spring break changes
2021-03-17 14:11:37 -04:00
Ross Thompson
0e2352a6de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21
Added possibly working OSU test bench as a precursor to running a bp benchmark.
...
Fixed a few bugs with the function radix.
2021-03-17 11:06:32 -05:00
Noah Boorstin
45ed2742cf
busybear: add seperate message on bad memory access becasue its confusing
2021-03-16 21:42:26 -04:00
Domenico Ottolia
c9d70a1778
Add privileged testbench
2021-03-16 20:28:38 -04:00
Shreya Sanghai
a79e26f9d8
added global history branch predictor
2021-03-16 16:06:40 -04:00
Noah Boorstin
6d8bcfe6bf
copy Ross's branch predictor preload change into busybear
2021-03-15 18:27:27 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Ross Thompson
0edaa625e3
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-12 20:16:03 -06:00
Ross Thompson
ccaaa829ce
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
David Harris
4465854423
Drafted rv32a tests
2021-03-12 00:06:23 -05:00
David Harris
d4e84c58ed
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
Ross Thompson
b1d1f3995c
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 17:12:21 -06:00
Noah Boorstin
f31d7a7f5c
busybear: account for CSR moving
2021-03-11 06:45:14 +00:00
Ross Thompson
f1f7884e10
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-10 15:37:02 -06:00
Ross Thompson
149c9aa0f2
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Ross Thompson
4d7e926dbb
I finally think I got the function radix debugger working across both 32 and 64 bit applications.
2021-03-10 14:43:44 -06:00
Ross Thompson
7b7cacbaf0
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 11:00:51 -06:00
David Harris
0baa004bb4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-09 09:28:32 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Noah Boorstin
87e2a9b920
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
9274d09ae2
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
1fc00d41c2
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
Noah Boorstin
f0a103687e
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
464c1de03d
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Ross Thompson
7902c3fdb6
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Noah Boorstin
cfcd7d1518
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Noah Boorstin
fde94f9057
Merge branch 'main' into busybear
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Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
bbracker
7852d866ef
JALR testing
2021-03-04 10:37:30 -05:00
Teo Ene
27a807db95
Added stop to coremark_bare testbench
2021-03-04 07:47:07 -06:00
Teo Ene
2723b21988
Linux CoreMark and baremetal CoreMark split into two separate tests/configs
2021-03-04 07:44:33 -06:00
