Teo Ene
5e5e03c717
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
Teo Ene
f69b84fe31
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-01-29 15:04:51 -06:00
Teo Ene
af5a068b5d
Synth automatically globs all available verilog files now, instead of requiring manual file listing
2021-01-29 15:04:43 -06:00
David Harris
6d5b01357d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Teo Ene
f0bbd71874
Added AHBW to rv32ic config file as well
2021-01-29 12:29:08 -06:00
Noah Boorstin
7183910c84
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
David Harris
4687d6998a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 01:07:22 -05:00
David Harris
e4e95bf941
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
Noah Boorstin
0fa7cffb11
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
Noah Boorstin
84e4193db6
busybear testbench: test on first 100k instrs
...
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
2021-01-29 00:14:23 -05:00
David Harris
aedadb7703
Renamed modules in privileged unit
2021-01-28 23:21:12 -05:00
David Harris
70554b94c3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 21:40:57 -05:00
David Harris
004cc525e2
Hint to optimize ifu
2021-01-28 21:40:48 -05:00
Noah Boorstin
c4964352f0
busybear: simulate first 10k instructions
...
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
2021-01-28 19:44:58 -05:00
Noah Boorstin
96ceac0e80
busybear: fix misaligned writing checking
2021-01-28 19:35:09 -05:00
Noah Boorstin
df1d174aea
busybear: add more test instructions
...
currently testing first 1k instrs
2021-01-28 16:41:37 -05:00
Noah Boorstin
9c0580f2e1
oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench
2021-01-28 16:35:12 -05:00
Noah Boorstin
cbab07967a
more of the same fixes
2021-01-28 16:26:15 -05:00
Noah Boorstin
03cea6e29b
more misaligned read fixing
...
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
2021-01-28 16:14:35 -05:00
David Harris
3e786729ac
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 15:44:14 -05:00
David Harris
1ad69b52d5
Fixed floating signals in clint and ieu
2021-01-28 15:44:05 -05:00
Noah Boorstin
e65166bec5
busybear testbench: understand bytemask for writes
2021-01-28 15:42:47 -05:00
Noah Boorstin
699bc7e195
Make gdb output parser understand other varients of load/store
2021-01-28 15:35:41 -05:00
David Harris
8eebf01dca
Fixed c.jr instruction improperly writing ra
2021-01-28 15:18:23 -05:00
Noah Boorstin
9a45b49536
busybear: ret is only 1 word
2021-01-28 14:47:40 -05:00
Noah Boorstin
5a5237b908
add speculative exception for compressed instructions
2021-01-28 14:40:35 -05:00
Noah Boorstin
632fecf43a
testbench now understands lw not aligned to 8 bytes
...
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
2021-01-28 13:33:22 -05:00
Noah Boorstin
e19af0a52a
busybear testbench: check for read data address also
...
and check for more end of files better
2021-01-28 13:16:38 -05:00
Noah Boorstin
7fd73d12e9
update busybear testbench to conform to new structure
2021-01-28 01:21:47 -05:00
Noah Boorstin
be3d024527
Busybear test now processes first 100 instrs correctly!
...
- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
ed85fda42a
fix memory write address decoding for busybear tests
2021-01-28 01:19:26 -05:00
David Harris
52d6a01cea
Created DCU and moved memdp into DCU
2021-01-28 01:03:12 -05:00
David Harris
01e37210ea
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 00:22:11 -05:00
David Harris
af25784b61
Provided PC + 2 or 4 (PCLink) for JAL
2021-01-28 00:22:05 -05:00
Noah Boorstin
840528a05f
update busybear testbench to conform to new structure
2021-01-27 23:42:19 -05:00
David Harris
9d821aab0f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 22:49:55 -05:00
David Harris
37a58cea17
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-27 22:49:47 -05:00
Noah Boorstin
74e57a8472
update busybear testbench to conform to new structure
2021-01-27 12:54:09 -05:00
David Harris
db5f45c240
Moved privileged unit from datapath to hart
2021-01-27 07:46:52 -05:00
David Harris
092edf953e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 06:40:39 -05:00
David Harris
4318629b32
Repartitioned datapath and controller into ieu
2021-01-27 06:40:26 -05:00
Noah Boorstin
91564c7ab1
show instruction assembly in waveform
2021-01-26 12:34:12 -05:00
Noah Boorstin
91dcffa26f
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
Noah Boorstin
09c92a6b5d
Fixed mem write checking
...
now passes around 50 instructions!
2021-01-25 20:07:08 -05:00
Noah Boorstin
05d4f2d33d
fix speculation ignoring for PC fetching
2021-01-25 20:07:06 -05:00
David Harris
b7988e536f
Reset Vector moved to config file
2021-01-25 15:57:36 -05:00
Teo Ene
a54070d074
Added synth and PnR flow
2021-01-25 14:28:14 -06:00
David Harris
bf07ec92b5
Added test configurations
2021-01-25 11:28:43 -05:00
Noah Boorstin
1d71282332
small busybear testbench changes
2021-01-24 20:43:47 -05:00
