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Configurable RISC-V Processor
72 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
c4964352f0
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Noah Boorstin c4964352f0 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
2021-01-28 19:44:58 -05:00
riscv-o3@a13ac64fa5 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined busybear: simulate first 10k instructions 2021-01-28 19:44:58 -05:00
.gitignore Busybear test now processes first 100 instrs correctly! 2021-01-28 01:19:27 -05:00
.gitmodules Added synth and PnR flow 2021-01-25 14:28:14 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor