Katherine Parry
|
97e7e619d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
cturek
|
0dc30a0acf
|
F Selection
|
2022-07-08 21:53:52 +00:00 |
|
Katherine Parry
|
c56fdd7e0f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-08 12:30:50 -07:00 |
|
Katherine Parry
|
88b4f9b40a
|
renamed signals in cvt and prostproc
|
2022-07-08 12:30:43 -07:00 |
|
James Stine
|
99fed5d59f
|
Update SRAM to /proj/wally
|
2022-07-08 08:09:55 -05:00 |
|
David Harris
|
8be1dafbd6
|
Removed testbench code that ignores mismatch on zero signatures
|
2022-07-08 09:17:31 +00:00 |
|
David Harris
|
87ea95e6c5
|
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-08 09:09:07 +00:00 |
|
David Harris
|
5ae88dbef0
|
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
|
2022-07-08 09:09:02 +00:00 |
|
David Harris
|
96cc66d151
|
Adjusting byte writes to RAM
|
2022-07-08 08:45:21 +00:00 |
|
David Harris
|
38ef8eebbb
|
Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
|
2022-07-08 08:44:37 +00:00 |
|
David Harris
|
234175f236
|
Removed unused swbytemask from CLINT
|
2022-07-08 08:43:24 +00:00 |
|
Katherine Parry
|
b67792086c
|
moved unsused division code again
|
2022-07-07 16:41:26 -07:00 |
|
cturek
|
ccc97d6fee
|
Sqrt exponents
|
2022-07-07 23:34:56 +00:00 |
|
Katherine Parry
|
2e772dee69
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-07 16:29:44 -07:00 |
|
Katherine Parry
|
b1e2a1e5a1
|
Revert "moved old divsqrt to unusedsrc"
This reverts commit 5dd07c76bd.
|
2022-07-07 16:29:17 -07:00 |
|
DTowersM
|
4786fb9fd6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-07 23:11:35 +00:00 |
|
DTowersM
|
aa8580b2dc
|
new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
|
2022-07-07 23:11:02 +00:00 |
|
Katherine Parry
|
5dd07c76bd
|
moved old divsqrt to unusedsrc
|
2022-07-07 16:09:56 -07:00 |
|
Katherine Parry
|
75a8cea4e4
|
srt divider merged into fpu
|
2022-07-07 16:01:33 -07:00 |
|
cturek
|
010ab2e90e
|
Seventeen Square Root Tests
|
2022-07-07 22:48:46 +00:00 |
|
David Harris
|
425fec0f41
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-07 22:00:59 +00:00 |
|
Katherine Parry
|
c581fba4aa
|
modified wally shared
|
2022-07-07 21:59:43 +00:00 |
|
David Harris
|
f865994ba1
|
fixing port errors
|
2022-07-07 21:57:10 +00:00 |
|
Katherine Parry
|
7771f7b3eb
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|
cturek
|
269884b672
|
Preprocessing for square root
|
2022-07-07 21:23:30 +00:00 |
|
David Harris
|
f2915129ab
|
Preliminary SRAM integration
|
2022-07-07 19:56:20 +00:00 |
|
David Harris
|
bf5168873e
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-07 15:51:33 +00:00 |
|
slmnemo
|
261248538c
|
sim-buildroot-batch now runs wally-pipelined-batch
with option buildroot buildroot-no-trace to boot linux from step 0
|
2022-07-06 18:06:43 -07:00 |
|
David Harris
|
8ae7139545
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-06 23:44:47 +00:00 |
|
DTowersM
|
5dfff900b1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
|
2022-07-06 23:44:27 +00:00 |
|
DTowersM
|
67c5d66209
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
|
2022-07-06 23:43:57 +00:00 |
|
David Harris
|
21fb120aac
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-06 23:43:05 +00:00 |
|
Ross Thompson
|
d716c25275
|
Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
|
2022-07-06 18:34:30 -05:00 |
|
Madeleine Masser-Frye
|
ad29e19a27
|
fixed width mismatch for rv64 ieuadrM and readdatawordM
|
2022-07-06 22:39:35 +00:00 |
|
David Harris
|
529f48ed58
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-06 13:26:26 +00:00 |
|
David Harris
|
76302a8599
|
PLIC and UART passing tests on APB
|
2022-07-06 13:26:14 +00:00 |
|
Madeleine Masser-Frye
|
52562c9190
|
new priority onehot module for better area/time
|
2022-07-06 00:08:59 +00:00 |
|
Madeleine Masser-Frye
|
b5454f3a55
|
took first match out of pmpadrdec
|
2022-07-06 00:02:01 +00:00 |
|
Madeleine Masser-Frye
|
d8ea12c6f4
|
fixed concatenation syntax
|
2022-07-05 22:36:54 +00:00 |
|
cturek
|
2faa8847f4
|
Radix 2 Integer division working (without signs or remainder)
|
2022-07-05 21:34:49 +00:00 |
|
David Harris
|
72e216d053
|
APB CLINT passing regression
|
2022-07-05 15:51:35 +00:00 |
|
David Harris
|
5f5ad77d4a
|
Modified uncore to use AHB bridge to GPIO
|
2022-07-05 05:02:21 +00:00 |
|
David Harris
|
c8ac05ba7b
|
AHB bridge for gpio
|
2022-07-05 05:01:59 +00:00 |
|
David Harris
|
ca95b46de5
|
Added reference to Schmookler01 for LOA
|
2022-07-05 05:01:12 +00:00 |
|
David Harris
|
1a356312b2
|
Added comments to PLIC about likely bug
|
2022-07-05 05:00:29 +00:00 |
|
David Harris
|
abfd935e06
|
removed delay in ahblite
|
2022-07-05 04:59:28 +00:00 |
|
David Harris
|
f5bdbbe219
|
Removed sig4 spurious message from testbench
|
2022-07-05 03:27:14 +00:00 |
|
David Harris
|
1bf701d958
|
Added check to halt testbench on failing to find file
|
2022-07-05 02:28:59 +00:00 |
|
Katherine Parry
|
2fc795ca70
|
added missing files
|
2022-07-03 21:40:47 -07:00 |
|
Katherine Parry
|
8ac722f693
|
Renaming signals to match chapter
|
2022-07-03 12:26:22 -07:00 |
|
David Harris
|
0fa35acbc5
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-02 19:37:14 +00:00 |
|
David Harris
|
89b319aa1b
|
FMA ZAligned name
|
2022-07-02 19:35:13 +00:00 |
|
Katherine Parry
|
8930cdcfbb
|
some prostprocessing cleanup
|
2022-07-01 14:55:46 -07:00 |
|
slmnemo
|
454facc1cd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-29 13:40:15 -07:00 |
|
slmnemo
|
39831e3a40
|
./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000
|
2022-06-29 13:40:11 -07:00 |
|
Daniel Torres
|
d1eebac73f
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
|
Daniel Torres
|
2ae22ac6cb
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
Katherine Parry
|
8f98f3bfab
|
added rv32 double precision stores - untested
|
2022-06-28 21:33:31 +00:00 |
|
Katherine Parry
|
d13a4c3378
|
removed an adder out of early termination
|
2022-06-28 18:01:11 +00:00 |
|
slmnemo
|
228028c837
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
Katherine Parry
|
071abc9d82
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-28 00:16:36 +00:00 |
|
Katherine Parry
|
0417a6a45b
|
very basic early termination passes testfloat 64-bit tests
|
2022-06-28 00:16:22 +00:00 |
|
cturek
|
7249295f53
|
Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work.
|
2022-06-27 23:55:21 +00:00 |
|
cturek
|
487553077f
|
Added int tests
|
2022-06-27 21:44:06 +00:00 |
|
Katherine Parry
|
a5fb60eb1a
|
radix-4 early termination working for special cases - not working completely
|
2022-06-27 20:43:55 +00:00 |
|
Katherine Parry
|
adaee899bb
|
radix-4 divider passing all double precision testfloat tests
|
2022-06-27 17:04:51 +00:00 |
|
Katherine Parry
|
70a1bb8377
|
fixed commented out error and removed killprod from result selection
|
2022-06-25 01:42:23 +00:00 |
|
Katherine Parry
|
fa1623551c
|
passing regression again
|
2022-06-25 00:31:32 +00:00 |
|
Katherine Parry
|
6d6cc7bb48
|
commented out error - also some divider bugs fixed
|
2022-06-25 00:04:53 +00:00 |
|
Katherine Parry
|
43882d5878
|
modified result select to account for x/inf
|
2022-06-24 21:23:15 +00:00 |
|
Katherine Parry
|
a85a868b56
|
radix 4 division denormal result handeling
|
2022-06-24 21:02:50 +00:00 |
|
Katherine Parry
|
9eefba5b58
|
added denormal input handeling - radix 4
|
2022-06-24 19:41:40 +00:00 |
|
Katherine Parry
|
b5c20bf112
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-24 01:09:53 +00:00 |
|
Katherine Parry
|
ff1fae74d8
|
division by zero added
|
2022-06-24 01:09:44 +00:00 |
|
slmnemo
|
6cbd7f4f6e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-23 16:51:51 -07:00 |
|
slmnemo
|
528869ef14
|
Removed references to initialization files
|
2022-06-23 16:50:27 -07:00 |
|
Katherine Parry
|
ec2c446c7e
|
forgot a file
|
2022-06-23 23:01:30 +00:00 |
|
Katherine Parry
|
b16e55906a
|
div debug - accounted for 1 bit normalization in exponent calculation
|
2022-06-23 22:59:43 +00:00 |
|
Katherine Parry
|
749d405da8
|
lint warning fix
|
2022-06-23 22:37:44 +00:00 |
|
Katherine Parry
|
de71773d69
|
added radix-4 0/d handling
|
2022-06-23 22:36:19 +00:00 |
|
slmnemo
|
851335ac98
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-23 14:39:59 -07:00 |
|
slmnemo
|
bca8fe1694
|
Removed big64.txt reference, fixing a warning
|
2022-06-23 14:39:53 -07:00 |
|
Katherine Parry
|
a5fc6757a1
|
generate qsel4 in verilog
|
2022-06-23 21:38:04 +00:00 |
|
slmnemo
|
3a471ac7d6
|
Added wally32periph to regression
|
2022-06-23 14:37:18 -07:00 |
|
David Harris
|
44216b3967
|
Fixed typo in clint
|
2022-06-23 21:27:46 +00:00 |
|
David Harris
|
d969edeb99
|
Reset mtimecmp in clint
|
2022-06-23 21:20:55 +00:00 |
|
James Stine
|
4ff866b39e
|
Update
|
2022-06-23 11:59:05 -05:00 |
|
James Stine
|
fe1b7a67cb
|
Add sqrt qlsc table generator
|
2022-06-23 11:46:44 -05:00 |
|
Katherine Parry
|
d7a363aaa7
|
fixt lint error
|
2022-06-23 16:11:50 +00:00 |
|
Katherine Parry
|
1612daa294
|
Testfloat running division - not passing
|
2022-06-23 00:07:34 +00:00 |
|
slmnemo
|
48c65db35c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 16:10:25 -07:00 |
|
slmnemo
|
09a633d7d1
|
changed order of makefiles and fixed warnings when running makes
|
2022-06-21 16:10:18 -07:00 |
|
David Harris
|
a2814898c8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-21 22:56:02 +00:00 |
|
David Harris
|
ac5dfc41f1
|
Trimmed lint-wally
|
2022-06-21 22:56:01 +00:00 |
|
slmnemo
|
6ba3a7615c
|
added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles
|
2022-06-21 15:54:24 -07:00 |
|
Katherine Parry
|
6001956bd8
|
using memread for quotent select
|
2022-06-21 15:49:52 -07:00 |
|
Katherine Parry
|
03b9878005
|
removed rv64fp from lint
|
2022-06-21 15:48:47 -07:00 |
|
David Harris
|
d865a1ce95
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-21 22:45:28 +00:00 |
|
Daniel Torres
|
1fab7605f5
|
fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely
|
2022-06-21 15:39:04 -07:00 |
|
Madeleine Masser-Frye
|
6229779b97
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-21 20:31:06 +00:00 |
|
Madeleine Masser-Frye
|
3c08861479
|
switched comparator to dc flip version
|
2022-06-21 20:30:33 +00:00 |
|
James Stine
|
b1f12f3345
|
Add hex output in bad but okay way
|
2022-06-21 15:07:24 -05:00 |
|
James Stine
|
ca0815ce0d
|
Add MATLAB scripts for PD plot
|
2022-06-21 10:14:53 -05:00 |
|
slmnemo
|
80a57d0469
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
b2cea45de0
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
0c6d36bbb2
|
made fixes to radix-2 divider testbench - divider doesn't pass
|
2022-06-20 23:01:53 +00:00 |
|
Katherine Parry
|
a0abfdefe6
|
radix-4 divider passing tests
|
2022-06-20 22:56:08 +00:00 |
|
Katherine Parry
|
03d823f5d7
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
James Stine
|
46bf9c351c
|
Update C program for r=4 division by recurrence to match Table in EL
|
2022-06-20 11:32:40 -05:00 |
|
Daniel Torres
|
397783812d
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1d4c543f71
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
0ede7c412e
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
475220a5ff
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
David Harris
|
a911077a01
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-17 15:45:24 +00:00 |
|
Katherine Parry
|
2a8c17170c
|
hopefully fixed lint error
|
2022-06-17 00:14:39 +00:00 |
|
Katherine Parry
|
c9cbf6082d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-15 22:58:42 +00:00 |
|
Katherine Parry
|
0ffaec850b
|
postprocess out of fpu critical path
|
2022-06-15 22:58:33 +00:00 |
|
Madeleine Masser-Frye
|
154a1c80c1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-06-15 18:30:27 +00:00 |
|
Madeleine Masser-Frye
|
84256924e7
|
cleanup, plots for paper
|
2022-06-15 18:28:36 +00:00 |
|
James Stine
|
c660403ff2
|
Add back SV for integer division to use 8-bit CPA in qslc
|
2022-06-15 11:46:39 -05:00 |
|
James Stine
|
a078015271
|
Add r=4 C code
|
2022-06-15 11:44:09 -05:00 |
|
Katherine Parry
|
08b2481917
|
some synth fpu optimizations
|
2022-06-14 23:58:39 +00:00 |
|
David Harris
|
f6e52c7f08
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
|
Katherine Parry
|
8e19331ad5
|
removed false critical path from fpu
|
2022-06-14 16:50:46 +00:00 |
|
Katherine Parry
|
674c31ce59
|
fixed acciedental critical path in FPU
|
2022-06-14 00:02:38 +00:00 |
|
DTowersM
|
7c0f4dd954
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 23:34:35 +00:00 |
|
DTowersM
|
39ed36d0ba
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
|
Katherine Parry
|
5f7072bd96
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
David Harris
|
802bfd74fb
|
Cleanup on RAM module
|
2022-06-13 19:37:43 +00:00 |
|
David Harris
|
3c44b5842b
|
Typo in gpio reset
|
2022-06-13 19:37:05 +00:00 |
|
slmnemo
|
3626d5880e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:30:33 -07:00 |
|
David Harris
|
9e1ec0255f
|
Removed SRT testvectors from repo
|
2022-06-13 19:27:33 +00:00 |
|
slmnemo
|
05a217c7e7
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-13 12:27:23 -07:00 |
|
slmnemo
|
c5d2037a7f
|
Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
|
2022-06-13 12:26:18 -07:00 |
|
slmnemo
|
a21d731834
|
Added more comments
|
2022-06-13 12:26:08 -07:00 |
|
David Harris
|
9080e35e54
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-06-13 19:26:07 +00:00 |
|
David Harris
|
09d72a33c5
|
Fixed XOR logic in GPIO
|
2022-06-13 19:26:03 +00:00 |
|
slmnemo
|
9f4ca06f7f
|
Added comment about name of LSUBusInit/Lock signal
|
2022-06-13 10:56:02 -07:00 |
|
slmnemo
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a79737e95b
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Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
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2022-06-10 20:43:56 -07:00 |
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slmnemo
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d6a1ee1141
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Added comments to signals added so the bus is easier to analyze
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2022-06-10 20:30:04 -07:00 |
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slmnemo
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31852fdb19
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Fixed failed regression state by only enabling counting when doing cached operations
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2022-06-10 20:00:09 -07:00 |
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slmnemo
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0e10435fb6
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Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
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2022-06-10 19:10:01 -07:00 |
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Madeleine Masser-Frye
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032385aee3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-10 21:11:47 +00:00 |
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Madeleine Masser-Frye
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374dfd1fc2
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added 'd' suffix to muxes for data-critical synths
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2022-06-10 21:11:05 +00:00 |
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DTowersM
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a61d1ab087
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simplified coremark
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2022-06-10 19:15:17 +00:00 |
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slmnemo
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5ac17eca1d
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Passed Regression: Seems to work perfectly fine
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2022-06-09 18:21:13 -07:00 |
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slmnemo
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75dffe4dcc
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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slmnemo
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a4c7d1d936
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?
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2022-06-09 17:50:47 -07:00 |
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DTowersM
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d280f10a8d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-10 00:38:07 +00:00 |
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DTowersM
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4e5d7ec3d6
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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