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Configurable RISC-V Processor
580 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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David Harris 6e298962e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-14 23:41:23 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Remove imem from testbenches 2021-04-14 20:20:34 -04:00
.gitignore busybear: stop NOPing out atomics 2021-03-25 13:29:56 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md

README.md

riscv-wally

Configurable RISC-V Processor