Ross Thompson
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1ceea51d8b
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Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
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2023-05-31 16:51:00 -05:00 |
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Ross Thompson
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a963f0af3a
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Updated source code to be compatible with verilator 5.011 for lint only.
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2023-05-31 10:44:23 -05:00 |
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Ross Thompson
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1315a0bf4a
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Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
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2023-05-26 16:00:14 -05:00 |
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Jacob Pease
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40f81d5da6
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The Vivado-RISC-V SDC works. Wally is now booting through it.
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2023-05-26 15:42:33 -05:00 |
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Ross Thompson
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b517a96261
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Update top level parameterized. Simulation slowed down to 4.5 minutes.
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2023-05-26 12:13:11 -05:00 |
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Ross Thompson
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8cf38b28aa
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The privileged unit is parameterized using Lim's method.
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2023-05-26 12:03:46 -05:00 |
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Ross Thompson
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02a788a083
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PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
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2023-05-26 11:06:48 -05:00 |
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Ross Thompson
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fcb1c63f5f
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Partial parameterization into mmu.
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2023-05-24 16:12:41 -05:00 |
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Ross Thompson
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5f5f33787d
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MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.
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2023-05-24 15:01:35 -05:00 |
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Ross Thompson
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1299319d0b
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More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.
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2023-05-24 14:56:02 -05:00 |
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Ross Thompson
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b91b54589e
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Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
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2023-05-24 14:05:44 -05:00 |
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Ross Thompson
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930fb67308
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Trying to figure out why the parameterization slowed down modelsim so much.
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2023-05-24 12:44:42 -05:00 |
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Jacob Pease
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b796b1b492
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Build doesn't work. AXI Crossbar has problems.
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2023-04-06 16:01:58 -05:00 |
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Ross Thompson
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da9cf02ba0
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-04-05 14:55:12 -05:00 |
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Ross Thompson
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394f2d65f2
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Progress on bug 203.
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2023-04-05 13:20:04 -05:00 |
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David Harris
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4552f9cf8c
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Fixed WFI to commit when an interrupt occurs
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2023-04-04 09:32:26 -07:00 |
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Ross Thompson
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0afba56927
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Updated GPIO signal names to reflect book.
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2023-03-24 18:55:43 -05:00 |
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Ross Thompson
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46b1bca4fc
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Fixed all tap/space issue in RTL.
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2023-03-24 17:32:25 -05:00 |
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Jacob Pease
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2d0199a354
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Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore
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2023-03-24 17:01:27 -05:00 |
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David Harris
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e03a533775
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Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault
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2023-03-22 06:29:30 -07:00 |
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David Harris
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a1eccf37dc
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Fix Issue 145
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2023-03-22 04:33:14 -07:00 |
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David Harris
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6922298f21
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Replaced FenceM with InvalidateICacheM for event counting of fence.i
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2023-03-18 09:24:31 -07:00 |
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Ross Thompson
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31fcc0daf7
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Renamed PCFSpill to PCSpillF.
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2023-03-06 17:50:57 -06:00 |
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Ross Thompson
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0cb5369351
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Renamed BTB misprediction to BTA.
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2023-03-03 00:18:34 -06:00 |
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Ross Thompson
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5b5677ccb8
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Added divide cycle counter.
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2023-03-02 23:59:52 -06:00 |
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Ross Thompson
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aabb454d1c
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Added the i and d cache cycle counters.
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2023-03-02 23:54:56 -06:00 |
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Ross Thompson
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cfca77172e
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Added fence counter.
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2023-03-02 23:29:20 -06:00 |
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Ross Thompson
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a313b10912
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Added store stall to performance counters.
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2023-03-02 23:10:54 -06:00 |
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Ross Thompson
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b98e007a53
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Cleaned up branch predictor performance counters.
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2023-03-01 17:05:42 -06:00 |
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Ross Thompson
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a6917d07f3
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Name cleanup.
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2023-02-28 17:48:58 -06:00 |
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Ross Thompson
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2ebe600f54
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Name changes to reflect diagrams.
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2023-02-28 15:37:25 -06:00 |
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Ross Thompson
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bc5aecf948
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-27 09:48:03 -06:00 |
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David Harris
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cf8b5f0783
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Added support for ZMMUL
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2023-02-27 07:29:53 -08:00 |
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Ross Thompson
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318189e5e6
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Signal name changes.
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2023-02-27 00:39:19 -06:00 |
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David Harris
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21b28fd1bb
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Renamed DAPageFault to UpdateDA
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2023-02-26 17:51:45 -08:00 |
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Ross Thompson
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72be4318b8
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-26 12:06:06 -06:00 |
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David Harris
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35653a18b7
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Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
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2023-02-26 09:38:32 -08:00 |
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Ross Thompson
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8bd4a4c35b
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Renamed signals to match new figures.
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2023-02-24 19:51:47 -06:00 |
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David Harris
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f0566173e6
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-21 09:58:18 -08:00 |
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David Harris
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a445e53e8d
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Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.
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2023-02-21 09:32:17 -08:00 |
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Ross Thompson
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545af7697f
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Simiplified BTB.
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2023-02-20 15:39:42 -06:00 |
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Ross Thompson
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6fbca64eb7
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Experimental branch prediction optimization.
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2023-02-10 15:45:56 -06:00 |
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Ross Thompson
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ca0eb5a591
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Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic.
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2023-02-10 10:33:10 -06:00 |
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David Harris
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78eb90715c
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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