Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
bf397f791f
Change all SUPPORTED type localparamters to one bit logic. Update configs for consistency.
2024-05-14 16:24:26 -07:00
Jordan Carlin
1065b8977a
Fix Q_SUPPORTED on derived configs
2024-05-14 11:49:54 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
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- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
ce5390de9c
Fixed UNCORE_RAM_RANGE for rv64i so VCS doesn't choke
2024-05-08 19:29:36 -07:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
James E. Stine
171da97fe3
add config for K extensions (7 so far)
2024-02-22 12:12:56 -06:00
David Harris
bf7e20e846
IEEE754 derivatives for testfloat
2024-01-30 09:49:27 -08:00
David Harris
f37c7bb1f6
Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this
2024-01-30 06:27:18 -08:00
David Harris
32c102d89a
All deriv tests generated, use sim/make deriv
2024-01-29 14:34:42 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
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Progress towards verilator support.
2023-12-18 12:50:49 -06:00
Rose Thompson
95fc5f4a1c
Towards removing the FPGA config file.
2023-11-13 17:20:26 -06:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
naichewa
7dd3f24d6c
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
Rose Thompson
657409aec5
Addec ZICCLSM to config files and started on lsu instance.
2023-10-27 13:07:23 -05:00
David Harris
b76c371e45
Config file cleanup
2023-10-18 05:38:36 -07:00
naichewa
0ff9ce527d
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
1a6e57f8c0
Renamed wally-config to config in many comments
2023-10-16 13:49:09 -07:00
naichewa
d5d4f9d044
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
28752303be
Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there
2023-10-04 12:28:12 -07:00
Ross Thompson
f863cbf366
Actually fixed non-power of 2 issue with RAS.
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Added RAS swapping to branch predictor scripts and configurations.
2023-09-27 12:25:05 -05:00
David Harris
c6631ef808
Added N and PBMT bits to MMU PTE
2023-08-24 19:44:46 -07:00
David Harris
d58ece3d44
renamed test-shared.vh to config-shared.vh
2023-07-30 05:22:39 -07:00
Ross Thompson
0ae9e8bfde
Removed old sdc from all configs.
2023-07-24 15:55:22 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
af0e33209f
Removed QEMU from configurations.
2023-07-19 10:23:55 -05:00
Ross Thompson
b756b248b4
Wow. The newest version of Vivado does not like the enums as parameters.
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The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
David Harris
644afa16cd
Clean up privilege rs1 decoding and implement svinval as sfence.vma
2023-07-13 02:41:17 -07:00
Ross Thompson
85567841eb
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
87fb9a3e16
Deleted remaining old configs except fpga as I still need to create the parameterized version.
2023-06-15 14:08:13 -05:00
Ross Thompson
c7536663c0
Merge pull request #319 from davidharrishmc/dev
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Renamed Performance Counter extension
2023-06-09 21:21:45 -04:00
David Harris
b70b0c7c5e
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
David Harris
df96900aa1
Added named support for Zicntr and Zihpm
2023-06-09 09:35:51 -07:00
Ross Thompson
a8a8422557
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
Ross Thompson
1315a0bf4a
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Ross Thompson
0020d94b39
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
930fb67308
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
Ross Thompson
414c79b923
Updated configs for local branch history `defines.
2023-05-02 11:11:04 -05:00
David Harris
cf8b5f0783
Added support for ZMMUL
2023-02-27 07:29:53 -08:00
David Harris
35653a18b7
Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
2023-02-26 09:38:32 -08:00
Ross Thompson
7df3a84060
Renamed branch predictors and consolidated global and gshare predictors.
2023-02-20 18:42:37 -06:00
David Harris
472c7da399
New expression for BTB_SIZE to avoid error during sky90 synthesis
2023-02-20 04:02:00 -08:00
David Harris
d07c6386b2
Added BTB_SIZE parameter independent of BPRED_SIIZE
2023-02-19 20:13:50 -08:00
David Harris
5b370bdc0f
Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.
2023-02-16 07:37:12 -08:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
