Rose Thompson
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1acc3951c8
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More simplifications.
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2023-11-21 00:19:24 -06:00 |
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Rose Thompson
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1d811b085c
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More cleanup.
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2023-11-21 00:14:59 -06:00 |
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Rose Thompson
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d2a747bf3d
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cleanup.
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2023-11-20 23:59:40 -06:00 |
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Rose Thompson
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70eb110a9c
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More optimizations to simplify cmo logic.
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2023-11-20 22:13:31 -06:00 |
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Rose Thompson
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52ac07ce8d
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Removed the CMO_WRITEBACK state from the cache and unused signals.
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2023-11-20 20:56:30 -06:00 |
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Rose Thompson
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5fb3c83efc
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Removed the CMO_WRITEBACK state from the cache.
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2023-11-20 20:52:11 -06:00 |
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Rose Thompson
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667fe035c0
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Simplified CMO.Zero fsm implementation slightly.
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2023-11-20 17:01:43 -06:00 |
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David Harris
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739c7f3f1c
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Merge pull request #491 from ross144/main
Running ImperasDV Linux is upto date
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2023-11-20 10:28:05 -08:00 |
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Rose Thompson
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eed6f11df6
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-20 11:29:45 -06:00 |
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Rose Thompson
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23e05cb8b2
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Finally have the cbo way muxing controls reduced to something sane.
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2023-11-20 11:28:03 -06:00 |
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Rose Thompson
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b137759b45
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-20 10:34:36 -06:00 |
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Rose Thompson
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64e627841a
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-20 10:30:42 -06:00 |
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Rose Thompson
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3594c08d4b
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Modified linux imperas tests to
1. enable zicclsm
2. enable logging at 7000 ms
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2023-11-20 10:30:35 -06:00 |
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Rose Thompson
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17e91f31f6
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Merge pull request #490 from davidharrishmc/dev
Synthesis running for textbook, preload IROM to avoid it being optimized out, updated M tests in risk-arch-test
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2023-11-19 20:42:29 -08:00 |
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David Harris
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8cb433cb66
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Commented IROM preloading
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2023-11-19 19:33:57 -08:00 |
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Rose Thompson
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cdd21d6635
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Added menvcfg to debugger for checking what linux has configured.
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2023-11-19 13:44:22 -06:00 |
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David Harris
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6fd32b6643
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-19 06:49:25 -08:00 |
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David Harris
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887cf935dc
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wallySynthAll.sh automates running all synthesis experiments without maxopt
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2023-11-19 06:49:07 -08:00 |
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David Harris
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b692c913c4
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Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile
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2023-11-18 20:56:50 -08:00 |
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David Harris
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acd8a63628
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Merge pull request #489 from ross144/main
fixes issue #487
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2023-11-18 19:22:33 -08:00 |
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Rose Thompson
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4ad7afcbf2
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Merge pull request #488 from JacobPease/main
FPGA Bootloader Preload From File
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2023-11-18 17:24:52 -08:00 |
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Jacob Pease
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a1e7158bd9
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Merge branch 'main' of github.com:openhwgroup/cvw
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2023-11-18 19:20:48 -06:00 |
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Jacob Pease
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87e6a5ccf2
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Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.
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2023-11-18 19:15:39 -06:00 |
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Rose Thompson
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efcd09c6cd
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-18 19:01:48 -06:00 |
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Rose Thompson
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8cbd3de413
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Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.
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2023-11-18 19:01:39 -06:00 |
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Rose Thompson
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4429732e8f
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Merge pull request #485 from davidharrishmc/dev
Wally sweep running again, embench sweep across configs
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2023-11-17 21:42:12 -08:00 |
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David Harris
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acc2db256f
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turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep
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2023-11-17 20:25:24 -08:00 |
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David Harris
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96556064a4
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Restored RV64GC BPRED_SIZE=10 for consistent synthesis results
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2023-11-17 18:31:44 -08:00 |
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David Harris
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423ae2bb76
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Ignore benchmark results
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2023-11-17 17:02:32 -08:00 |
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David Harris
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96f9409da4
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Embench Makefile to sweep experiments across configs
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2023-11-17 15:11:52 -08:00 |
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David Harris
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7b33331cf7
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Got Wally sweep running again
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2023-11-17 15:10:57 -08:00 |
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David Harris
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c500a7c057
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-17 14:26:55 -08:00 |
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David Harris
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0eb23569f5
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Merge pull request #480 from stineje/main
wrapper insertion automatically for Wally vs. individual PPA analysis
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2023-11-17 14:26:47 -08:00 |
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James E. Stine
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3dc7b93f57
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Revert removal of WRAPPER option that is not prudent
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2023-11-17 16:25:35 -06:00 |
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David Harris
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44ec6efdab
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-17 13:28:07 -08:00 |
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David Harris
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f4f389f373
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Initial version of embench_arch_sweep.py
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2023-11-17 13:27:57 -08:00 |
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David Harris
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70c58a8ce1
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Merge pull request #484 from ross144/main
Changed bpred-sim.py to only simulate 12 jobs at once.
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2023-11-17 13:26:24 -08:00 |
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Rose Thompson
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8cf2c404bf
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bpred-sim only simulates 12 jobs at once.
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2023-11-17 15:21:58 -06:00 |
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David Harris
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8baa5b2e7b
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Merge pull request #483 from ross144/main
Fixed branch predictor embench generation results
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2023-11-17 10:07:30 -08:00 |
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Rose Thompson
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d95d7130a3
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Fixed bugs in paraseHPMC.py
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2023-11-17 12:05:22 -06:00 |
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Rose Thompson
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38b327eaf8
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Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.
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2023-11-17 11:21:25 -06:00 |
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Jacob Pease
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38cf7f0fb7
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ahbsdc submodule actually added this time.
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2023-11-16 17:46:48 -06:00 |
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Jacob Pease
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9df87872ef
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Deleted vivado-risc-v directory and added ahbsdc.
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2023-11-16 15:13:12 -06:00 |
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Jacob Pease
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23e5fca2a7
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Merge branch 'main' of github.com:jacobpease/cvw
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2023-11-16 14:04:11 -06:00 |
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Jacob Pease
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ff73f798ed
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Replaced vivado-risc-v addins directory with new SDC repo.
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2023-11-16 13:59:12 -06:00 |
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Rose Thompson
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0b49c736b9
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Removed the size opt tests from the branch predictor analysis.
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2023-11-15 22:35:33 -06:00 |
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David Harris
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94201e993f
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Merge pull request #481 from ross144/main
Fixed the BTB logger so sim_bp correctly reports BTB performance
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2023-11-15 17:45:38 -08:00 |
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Rose Thompson
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21b2a71bd6
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Updates to btb logger processing.
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2023-11-15 16:53:44 -06:00 |
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Rose Thompson
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c4f4e0fbc0
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Added btb reference data.
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2023-11-15 16:39:35 -06:00 |
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Rose Thompson
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9a90c15f37
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Extended SeparateBranch to support both just branches and all control flow instructions.
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2023-11-15 16:36:49 -06:00 |
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