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649 Commits

Author SHA1 Message Date
David Harris
2cdd49c7d2 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
7024293a59 Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
66424a8246 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
866540580a SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
94459ade3d Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
25ad39939f put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
David Harris
8eee0c0ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
554c2b3550 Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
cb1a7d54a4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
4fbf78e049 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
9c4de0e9c1 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
dee32f70bf Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
bc123b5564 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
7e3f75a35d Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20 sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
Kip Macsai-Goren
e557e420b6 added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
5df381e26f renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c3ffcd0e95 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
3d1e1202f3 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
0e5cc40360 added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Skylar Litz
970f6c4222 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
594db170de fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
6e8b27de17 Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
ffd4713fd1 Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9042844b38 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
89cce88d33 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
0f4ca62157 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
8ad920fcb3 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
da29193f9b removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
7ff85258f0 added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
7fe33b2147 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
cf1fde62fb Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
0ede295e88 Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
851d5e8c5e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
16ad1e0cab Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
f1ddbb169c Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
03f84bf11c Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
7bc6943527 Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
5e76c83309 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
afc38abe08 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
8fcd4d47b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
165a36acac Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
5c607f2b6b Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
cd53163d9a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
080963c381 fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
510021af65 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
546ef08eb2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
1f7a95637a Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
a8ad7be246 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
1ba328324b Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
64698aa806 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
fd3920b217 replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
c3164f0ce1 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
a99466a487 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
4a7effaf9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
861fbd698b Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
c409bde6ae fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
2819a1c305 Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
812b56acc6 Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
de5b61291f Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Kip Macsai-Goren
1f9c987efe added new tests to makefrag and tests.vh 2022-04-17 21:00:36 +00:00
Ross Thompson
059c04e2a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
2436534687 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
83d283354c Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
238cc9f9fd Commented output power analysis to speed simulation. 2022-04-16 15:32:59 -05:00
Ross Thompson
16b3c64234 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
a28831b83e Added WFI to the testbench instruction name decoder 2022-04-14 17:12:11 +00:00
David Harris
855d68afde WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
bbracker
fe53dd1683 fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM 2022-04-14 09:23:21 -07:00
bbracker
eb21e34000 fix ReadDataM forcing 2022-04-13 15:32:00 -07:00
Ross Thompson
2e8afd071e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 13:39:47 -05:00
bbracker
5de92af0b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
735c75af55 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
52ed99ca1b improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
03f1c01f14 whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
d3e9703c19 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
bb6f1cf816 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
fc173a7954 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
ff826fdb02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
f995ec2a54 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
c3d9eafe60 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
aa71fe542d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
3b6cb5f0ba small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
Ross Thompson
2294cbc1c6 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
5e4682fb65 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
c307cff503 fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00