David Harris
e714b75888
LSU minor edits
2022-08-23 07:35:47 -07:00
David Harris
0e489443f2
Finished FPU-LSU interface cleanup
2022-08-22 13:43:04 -07:00
David Harris
8444eca57c
Simplified FPU-LSU interface to skip IEU
2022-08-22 13:29:20 -07:00
Ross Thompson
ebe4339953
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
2ba390adf4
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
797d9e3610
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
2022-08-01 21:12:25 -05:00
Ross Thompson
3cd8404917
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Ross Thompson
3612db2d70
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Ross Thompson
05484c4c05
signal name cleanup.
2022-07-22 23:36:27 -05:00
Katherine Parry
12a54161c0
found the bug in the store modification
2022-07-12 22:42:19 +00:00
Katherine Parry
62205ebb3b
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
David Harris
72e216d053
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
8f98f3bfab
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
03d823f5d7
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
slmnemo
be658d3933
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
a5aa75e5de
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
90c5e5d319
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
129fab3794
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
efce3e4953
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80965f953c
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
5acb526375
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
fb725a9e0a
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
462158ea92
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
2882460c94
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
Ross Thompson
b9a19304db
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
7a824eaae1
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
58668812c1
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-23 14:10:38 -05:00
Ross Thompson
c5be2cb1d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-22 21:28:50 -05:00
Ross Thompson
cec7625d91
Added comment about needed fix to misaligned fault.
2022-03-22 16:52:07 -05:00
Ross Thompson
d347de8c49
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616
cleanup of ram.sv
2022-03-11 18:09:22 -06:00
Ross Thompson
e802deb4d6
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
11e5aad38a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5
atomic cleanup.
2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445
Name changes.
2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
50789f9ddd
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
Ross Thompson
ed32801cc1
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
acd60218b8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
David Harris
48705457d5
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
Ross Thompson
6a52f95cc8
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
56fc6d0d7c
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
f48b12b089
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
ae06785b9f
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
27042f028e
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
c8e6884926
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
411997010b
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
911ee36b22
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
3cd067ac6a
Finished merge.
2022-02-08 11:36:24 -06:00
Ross Thompson
1766c0f5ba
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
Ross Thompson
c846368537
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
David Harris
e92461159d
cache cleanup
2022-02-03 15:36:11 +00:00
David Harris
9e0055cbb9
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
Ross Thompson
b05abc1795
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
d2ab17e1af
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
fa8914a830
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4
Moved lsu virtual memory logic into separate module.
2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Ross Thompson
d52c5b0393
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
147d71fd46
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
62e5c7fd13
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
22c84dcd80
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
Ross Thompson
4ecc2d029a
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
