178 Commits

Author	SHA1	Message	Date
Ross Thompson	8156109add	More cleanup.	2022-08-31 11:12:38 -05:00
Ross Thompson	89f13370e2	Removed old signals.	2022-08-31 09:50:39 -05:00
Ross Thompson	5409501ca6	Maybe fixed it?	2022-08-30 18:08:34 -05:00
Ross Thompson	8b9f30c91a	more progress.	2022-08-30 17:32:32 -05:00
Ross Thompson	315f662eb9	More progress.	2022-08-30 15:27:19 -05:00
Ross Thompson	637d60b64c	Progress.	2022-08-30 14:17:00 -05:00
Ross Thompson	8cf3c7b352	new cache bus fsm not working but lints. ... Forgot a few files in the last commit.	2022-08-30 10:58:07 -05:00
Ross Thompson	a2220fc142	Have a rough working multi manager!	2022-08-29 17:11:27 -05:00
Ross Thompson	f5584bb41c	Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.	2022-08-29 17:04:53 -05:00
Ross Thompson	233777f744	Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.	2022-08-29 13:01:24 -05:00
Ross Thompson	e805f33f4e	Typo.	2022-08-29 11:40:35 -05:00
Ross Thompson	e7de0e033e	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
Ross Thompson	7b76fbaa9a	Removed ignore request from busfsm.	2022-08-28 21:12:27 -05:00
Ross Thompson	122c88ee46	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
Ross Thompson	dd7736cb93	Possible fix.	2022-08-28 13:10:47 -05:00
Ross Thompson	a81fcc6b4b	Partial fix to bus + dtim.	2022-08-27 23:44:17 -05:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	60b673cafd	Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus	2022-08-27 05:31:56 -07:00
David Harris	812158aeee	Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each	2022-08-26 20:26:12 -07:00
David Harris	95dd50a567	Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem	2022-08-26 20:12:03 -07:00
David Harris	ca6837f597	Fixed endian swapping on bus only	2022-08-26 19:58:04 -07:00
David Harris	5f37e16b62	Fixed rv32e LSU and IFU issues	2022-08-25 20:02:38 -07:00
David Harris	671ea60f3e	lsu simplification	2022-08-25 18:52:42 -07:00
David Harris	f262abb5c3	Removed unused signals	2022-08-25 18:34:39 -07:00
David Harris	b73286ece6	Removed unused signals	2022-08-25 18:30:46 -07:00
David Harris	cfcde754c3	Removed CacheBusAck	2022-08-25 18:17:34 -07:00
David Harris	9bc62ce124	Removed SelUncachedAdr	2022-08-25 18:15:59 -07:00
David Harris	f39e62eeea	Removed Cache_Enabled	2022-08-25 18:13:34 -07:00
David Harris	85e93e2bb7	Removed CacheFetchLine and CacheWriteLine	2022-08-25 18:10:15 -07:00
David Harris	e485e986a5	Removed wordcount	2022-08-25 18:04:49 -07:00
David Harris	5340c45dfc	Separated busdp for cache from simpler logic for no cache	2022-08-25 17:54:04 -07:00
David Harris	9a92bfe095	Simplified swbytemask	2022-08-25 17:32:16 -07:00
Ross Thompson	5c2bc20dbd	Almost fixed issues with irom and dtim address selection.	2022-08-25 15:52:25 -05:00
Ross Thompson	f67010c688	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 14:40:52 -05:00
David Harris	bc0c7d0cd8	Cleaned up SelBusWord	2022-08-25 11:18:13 -07:00
David Harris	c442dea173	Removed M sufix from busdp signals	2022-08-25 11:13:01 -07:00
David Harris	48f346baf8	Renamed LSUFunct3M to Funct3 in busdp	2022-08-25 11:08:12 -07:00
David Harris	9bada9c14a	Renaming LSU signals from busdp	2022-08-25 11:05:10 -07:00
David Harris	3ba961d1a8	renamed BusBuffer to FetchBuffer	2022-08-25 10:44:39 -07:00
David Harris	dda3b441d7	Continued busdp/ebu simplification	2022-08-25 10:20:02 -07:00
David Harris	aba914ea5e	Renamed AHB signals coming out of LSU to LSH_<AHBNAME>	2022-08-25 09:52:08 -07:00
Ross Thompson	e605ef57dc	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
David Harris	ae0702d129	Renamed DCache to Cache in busdp/busfsm signal interface	2022-08-25 06:21:22 -07:00
David Harris	1206b388c7	Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM	2022-08-25 04:06:27 -07:00
David Harris	f7209627c2	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	51adf6cba9	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
David Harris	c61dba6192	Fixed LSU typos	2022-08-23 10:23:08 -07:00
Ross Thompson	aa5cbab0d8	Replaced LSU data replication with 0 extention.	2022-08-23 10:43:47 -05:00
Ross Thompson	3b07584403	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00