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Author	SHA1	Message	Date
Thomas Fleming	7f7cc73dd3	Update virtual memory tests and move to separate folder	2021-03-30 22:18:29 -04:00
Teo Ene	7c3963547d	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
David Harris	1158b3aa73	Added PPA README	2021-03-25 11:21:31 -04:00
Thomas Fleming	89a2fe5741	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
Thomas Fleming	95bf1e26b8	Add vscode and pycache folders to .gitignore	2021-03-25 02:37:50 -04:00
Thomas Fleming	4f01aae844	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-25 02:35:21 -04:00
bbracker	d52c71086a	added 1 tick delay to dtim flops	2021-03-25 02:23:30 -04:00
bbracker	5327dcfcc8	instrfaults not respecting stalls bugfix	2021-03-25 00:16:26 -04:00
bbracker	a8b7d7a248	upgraded gpio bus interface	2021-03-25 00:15:02 -04:00
bbracker	77768cee5d	gitignore FunctionRadix.addr	2021-03-25 00:13:46 -04:00
bbracker	3e656fc035	future work comment about suspicious-looking verilog in csri.sv	2021-03-25 00:10:44 -04:00
Thomas Fleming	f2604797fb	Add all PMP addr registers	2021-03-24 21:58:33 -04:00
Teo Ene	55c5d2ca23	Manual assembly hack to prevent RV64IM coremark from EBREAKing early	2021-03-24 18:05:34 -05:00
Teo Ene	1e691e120b	Fix typo from last commit	2021-03-24 17:09:58 -05:00
Teo Ene	9f44eb36ef	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-24 17:04:48 -05:00
Teo Ene	6a7b69ff2d	Updated coremark_bare testbench for IM	2021-03-24 17:04:43 -05:00
Katherine Parry	123e63b440	fixed various bugs in the FMA	2021-03-24 21:51:17 +00:00
Teo Ene	07f7df82e3	Added BPTYPE to coremark_bare config	2021-03-24 16:38:29 -05:00
Domenico Ottolia	3909158619	re-organize privileged tests to be in rv64p to rv32p folders	2021-03-24 13:51:25 -04:00
Katherine Parry	fb78dedae2	fixed various bugs in the FMA	2021-03-24 01:35:32 +00:00
Teo Ene	8556c07261	Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem	2021-03-23 15:21:13 -05:00
Shreya Sanghai	09b90557f7	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Jarred Allen	789c189260	Another tweak to regression-wally.py comments	2021-03-23 00:18:38 -04:00
Jarred Allen	2c4eda2ba3	Slight change to regression-wally.py comments	2021-03-23 00:02:40 -04:00
Noah Boorstin	43d23e3d9b	busybear: add better warning on illegal instruction ... ...also it seems that mret is being picked up as an illegal instruction??	2021-03-22 18:24:35 -04:00
Noah Boorstin	4160bf50b0	busybear: temporarially force rf[5] correct after failure to read CSR	2021-03-22 18:12:41 -04:00
Noah Boorstin	4be19421c4	busybear: allow overwriting read values	2021-03-22 17:28:44 -04:00
Noah Boorstin	b4166e9fd0	busybear: finally get the right error	2021-03-22 16:52:22 -04:00
bbracker	c3a6d6bf42	added delays to uart AHB signals	2021-03-22 15:40:29 -04:00
Noah Boorstin	7350b9f18f	busybear: comment out some debug printing	2021-03-22 14:54:05 -04:00
Noah Boorstin	c4fb51fad1	regression: expect 200k instead of 100k busybear instrs ... and a minor busybear bugfix	2021-03-22 14:47:52 -04:00
bbracker	eea7e2e47e	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Katherine Parry	9af0ad815c	fixed various bugs in the FMA	2021-03-21 22:53:04 +00:00
Katherine Parry	fd381e60d7	messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic	2021-03-20 02:05:16 +00:00
bbracker	df51d9908d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
Shreya Sanghai	804407eab7	fixed minor bugs in testbench	2021-03-18 17:37:10 -04:00
Shreya Sanghai	dfc86539cc	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	9386e6a524	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Ross Thompson	181a28e875	Fixed minor bug with the size of gshare.	2021-03-18 16:00:09 -05:00
Shreya Sanghai	f35d3b39c8	removed unnecesary PC registers in ifu	2021-03-18 16:31:21 -04:00
Thomas Fleming	859d242d81	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-18 14:36:42 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Thomas Fleming	f04e554e35	Improve page table creation in python file	2021-03-18 14:27:09 -04:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	fa1407f6e3	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Noah Boorstin	a226e24ed3	busybear: update memory map, add GPIO	2021-03-18 12:17:35 -04:00
Teo Ene	0ff785549e	Switched coremark to RV64IM	2021-03-17 22:39:56 -05:00
Teo Ene	db164462ed	adapted coremark bare testbench to new dtim RAM HDL	2021-03-17 16:59:02 -05:00
Teo Ene	29634f1475	Temporarily reverted my last few commits	2021-03-17 15:16:01 -05:00
Teo Ene	e6661ea26a	fix to last commit	2021-03-17 15:07:02 -05:00