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Configurable RISC-V Processor
423 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Thomas Fleming 95bf1e26b8 Add vscode and pycache folders to .gitignore
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sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor