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Configurable RISC-V Processor
396 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
eea7e2e47e
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bbracker eea7e2e47e first pass at PLIC interface
2021-03-22 10:14:21 -04:00
sky130
wally-pipelined first pass at PLIC interface 2021-03-22 10:14:21 -04:00
.gitignore Added debug option to disable the function radix if not needed. 2021-03-10 15:17:02 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor