Ross Thompson
7902c3fdb6
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Ross Thompson
5b7f0772ca
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 16:06:22 -06:00
Brett Mathis
b5a08e496f
Pipelined functional units for FPU
2021-03-04 14:30:11 -06:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
bbracker
7852d866ef
JALR testing
2021-03-04 10:37:30 -05:00
bbracker
5de23fcbe0
changed test maker to output trace files for debug
2021-03-04 10:36:04 -05:00
Ross Thompson
d0223da2f7
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1
Merge branch 'tlb_toy' into main
2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120
Move tlb into mmu directory
2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24
Fix to 32-bit option of commit 2d40898158
2021-03-04 01:33:34 -06:00
Thomas Fleming
d821a1dbfa
Merge branch 'main' into tlb_toy
2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956
Generalize tlb module
...
- number of tlb entries is now parameterized
- tlb now supports rv64i
2021-03-04 01:13:31 -05:00
Thomas Fleming
5fd521d333
Create virtual memory ad-hoc test
...
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
2021-03-03 17:06:37 -05:00
Teo Ene
d3a1afe50e
Fix to last push
2021-03-03 15:20:38 -06:00
Teo Ene
b50faef94d
Updated coremark .do file for easier debugging
2021-03-03 15:10:39 -06:00
Teo Ene
e30645a4f1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-02 17:23:44 -06:00
Teo Ene
d02e22feac
Updated coremark .do file for easier debugging
2021-03-02 17:23:39 -06:00
David Harris
23a1cf63b3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-01 00:09:55 -05:00
David Harris
6f4e8b723e
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Teo Ene
2d40898158
Properly implemented the fix from commit 5fee65231e
2021-02-28 22:22:04 -06:00
Noah Boorstin
a5f1dbfe23
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
Ross Thompson
c2cf3f9fb6
Updating the test bench to include a function radix. Not done.
2021-02-26 19:43:40 -06:00
David Harris
73920282af
Eliminated flushing pipeline on CSR reads
2021-02-26 17:00:07 -05:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
225102047a
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2
Retimed peripherals for AHB interface
2021-02-26 00:55:41 -05:00
Brett Mathis
87e4311339
Fcmp/Fsgn pipeline modules
2021-02-25 18:22:30 -06:00
David Harris
bad180fc15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2
Restored to working multiplier after Lab 2
2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf
FPU Assembly tests
2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b
Fixed previous commit
2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e
Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
2021-02-25 11:23:01 -06:00
Teo Ene
b9701293a0
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
Teo Ene
a6c16af721
Merge remote-tracking branch 'origin/lab3' into main
2021-02-25 10:28:20 -06:00
Teo Ene
8491deb1a9
Changed .do file back to run all
2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
eb52fd1c5a
removed WALLY ALU tests to avoid merge conflict with main branch
2021-02-25 00:15:22 -05:00
Teo Ene
cfd45a46c3
Added provisional coremark files from work with Elizabeth
2021-02-24 20:07:07 -06:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Katherine Parry
07641203ee
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-23 20:21:53 +00:00
Katherine Parry
906ec30339
inital FMA push
2021-02-23 20:19:12 +00:00
David Harris
7737b0f709
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8
Debugging Bus interface
2021-02-22 13:48:30 -05:00
Ross Thompson
c856003f73
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f
minor change to wave file.
2021-02-19 09:08:13 -06:00
