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Configurable RISC-V Processor
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Ross Thompson 6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. 2021-02-14 08:58:33 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor