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Author SHA1 Message Date
David Harris
5e1932c649 Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc 2022-09-21 04:55:43 -07:00
David Harris
f7d272c315 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00
David Harris
1cbdd20778 Restored radix 2 to pass regression 2022-09-20 19:30:16 -07:00
David Harris
3b98881c4e renamed u to udigit to avoid conflict with U 2022-09-20 19:29:23 -07:00
cturek
6e300a667e Fixed R4 Sqrt overshifting 2022-09-21 00:05:36 +00:00
cturek
c3c764f0ba Fixed fgen4 2022-09-20 20:00:01 +00:00
Ross Thompson
980b35d585 Merge branch 'tempMain' into main 2022-09-20 13:57:38 -05:00
Ross Thompson
1658edd21e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 11:56:53 -05:00
Ross Thompson
426ec6222b Added chip enables to sram. 2022-09-20 10:49:14 -05:00
David Harris
11fb39b373 Define LOGNORMSHIFTSZ 2022-09-20 08:31:57 -07:00
Ross Thompson
822d989383 Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
4c3c517322 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 09:47:16 -05:00
David Harris
00c15ec472 renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
David Harris
d01588d693 Removed D2 and D2b from radix2 stage 2022-09-20 04:20:38 -07:00
David Harris
2ea7df1b6d Simplified UM initialization 2022-09-20 04:18:12 -07:00
David Harris
0d5e80a4f0 fdivsqrtfgen4 comments 2022-09-20 04:13:21 -07:00
David Harris
653c458241 Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
David Harris
0ec1886b89 Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
David Harris
a05b6486b1 Simplified fdivsqrtpostproc QmM logic 2022-09-20 03:30:18 -07:00
David Harris
87cde2c427 make QmM size b+1 indpenedent of radix 2022-09-20 03:25:09 -07:00
David Harris
e455f41b97 clean up divshiftcalc 2022-09-20 03:19:50 -07:00
David Harris
211705eca2 clean up divshiftcalc 2022-09-20 03:17:29 -07:00
David Harris
d3b2a192eb clean up divshiftcalc 2022-09-20 03:13:11 -07:00
David Harris
f5083803c2 clean up divshiftcalc 2022-09-20 03:08:25 -07:00
David Harris
2faa0d14be Cleaning up divshiftcalc LOGNORMSHIFTSZ 2022-09-20 02:35:01 -07:00
Jacob Pease
1e7bbe1a87 Fixed rxfifotimeout restarting for every new character, even when already high. 2022-09-19 18:00:30 -05:00
cturek
019a6eb9f5 Radix 4 sqrt passing first two tests 2022-09-19 21:26:32 +00:00
Ross Thompson
bcca9a62c5 Fixed up IFU ahb interface names and widths. 2022-09-19 10:54:22 -05:00
David Harris
8e90862dad Removed EarlyTermShift from fdiv 2022-09-19 08:44:23 -07:00
David Harris
73ceb4590c Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
David Harris
3cf6becaf4 fdivsqrtiter simplification 2022-09-19 01:08:01 -07:00
David Harris
e840edc4e6 Reduced number of cycles needed for division 2022-09-19 01:02:04 -07:00
David Harris
d6f1453275 Cleaned up otfc4 2022-09-19 00:58:20 -07:00
David Harris
309995a6e9 OTFC simplification 2022-09-19 00:51:56 -07:00
David Harris
59b6346a28 Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
David Harris
e764d4322c fdiv cleanup 2022-09-19 00:32:34 -07:00
David Harris
cf0c20d489 Division working again for radix 2 with unified OTFC 2022-09-19 00:30:30 -07:00
David Harris
b636072914 Unified on-the-fly conversion working for radix 2; broke radix-4 division 2022-09-19 00:04:00 -07:00
David Harris
4dbe1035cb Added 2 bits to C to initialize properly 2022-09-18 22:44:22 -07:00
David Harris
f202eb0f6f Added 2 bits to C to initialize properly 2022-09-18 22:42:35 -07:00
David Harris
cff3c2535d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-18 21:27:36 -07:00
David Harris
498c053aab FP testbench 2022-09-18 21:27:21 -07:00
David Harris
f38bb5b32e Divide testfloat starts with half-precision tests 2022-09-18 06:46:47 -07:00
Ross Thompson
16e10a4c5b added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
57c366c1b2 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
Kip Macsai-Goren
9821a50eaa added mstatus uxl, sxl bit tests (not tested in regression yet) 2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
0cc7f5719c ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
c5cbe43732 Fixed typos in existing endianness test 2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
e6987524ab added full coverage of subword loads and stores to endianness test 2022-09-17 23:14:38 +00:00