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430 Commits

Author SHA1 Message Date
James Stine
c8921250db remove hard-code path in wave_config.wcfg even though its probably not needed. Its a generated file. I believe the path doesn't matter, so I removed it. 2024-09-18 15:40:00 -05:00
Rose Thompson
510e3a268c Added spi debugger to build script. 2024-09-05 12:04:14 -07:00
Rose Thompson
261e503061 Updates for arty A7 device tree. 2024-09-05 12:02:07 -07:00
Rose Thompson
8c99e28c8b Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script. 2024-09-03 21:03:38 -07:00
Rose Thompson
f22f056b09 This actually fixes the vcu108 to correctly set the SPI clock frequency. 2024-09-03 13:11:03 -07:00
Rose Thompson
c24d061d0a Fixed typo in fpga Makefile. 2024-09-03 12:19:16 -07:00
Rose Thompson
8248f2dd66 Added MAXSDCCLOCK to parameters set by the FPGA makefile. 2024-09-03 10:55:15 -07:00
Rose Thompson
d0ae6bf217 Fixed type in fpga Makefile 2024-09-03 10:36:49 -07:00
Rose Thompson
cde4598ed5 Updated vcu108 and vcu118 scripts to corrects set the clock speed. 2024-09-03 10:31:55 -07:00
Rose Thompson
702fa4e7bd Finally worked out that subtle bug in the tcl scripts clock setting. 2024-09-03 10:30:34 -07:00
Rose Thompson
e29e1feed5 Corrects merge error in Arty A7 clock speed. 2024-09-02 15:01:41 -07:00
Rose Thompson
8375e168c0 Removed file accidently readded. 2024-09-02 14:48:36 -07:00
Rose Thompson
3a0e28fea0 Added missing spi debugger. 2024-09-02 14:47:31 -07:00
Rose Thompson
4afdb500d7 Added missing files. 2024-09-02 14:46:41 -07:00
Rose Thompson
d5e0382a81 vcu108 build now starts with make vcu108 and selects the correct 
memory size, starting address, device tree location, and clock speed
for the zsbl and synthesis scripts.
 2024-09-02 14:23:16 -07:00
Rose Thompson
869860bc55 Merge branch 'main' of github.com:ross144/cvw 2024-09-02 14:08:48 -07:00
Rose Thompson
9471ccd2fc Updated Makefiles and source files to build the zsbl according to the config. 2024-09-02 14:03:47 -07:00
Rose Thompson
2e55f1cecc Well on the way to a fully automated FPGA build process which 
correctly sets the clocks and memory locations.
 2024-09-02 11:19:02 -07:00
Jacob Pease
4b8d35bd8a Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-30 14:18:54 -05:00
Jacob Pease
4acac08320 Fixed Arty constraints and corrected typos. 2024-08-30 14:17:37 -05:00
Rose Thompson
f1d9e18dee Modified fpga config to support two fpga boards with different amount of memory. 
Modified vcu108 constraints to better constrain the spi clock and in/out.
 2024-08-29 16:12:58 -07:00
Rose Thompson
0ce4d1b452 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-29 10:50:27 -07:00
Rose Thompson
7e16ddd859 Improved fpga synth script. 2024-08-27 15:50:05 -07:00
Rose Thompson
e5d3462a90 Converted wall.tcl to entirely project mode. 2024-08-27 14:15:58 -07:00
Jacob Pease
44ece7cb96 Added CVW header to spitest files. 2024-08-27 14:28:49 -05:00
Rose Thompson
f20a1564fa Added SPI debugger. 2024-08-26 17:22:13 -07:00
Jacob Pease
d649473ec8 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-24 21:57:44 -05:00
Jacob Pease
ad6734eb6d Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full. 2024-08-24 21:36:29 -05:00
Rose Thompson
ee1e09a6a2 VCU108 now boot linux at 50MHz! 2024-08-23 17:18:47 -07:00
Rose Thompson
14083bc642 VCU108 is not synthesizing at 50MHz. Still running into a few problems 
with the new SPI sd card device.
 2024-08-23 16:17:15 -07:00
Rose Thompson
842aea157c Updated vc108 constraints for spi based sd card and setting 50 Mhz. 2024-08-23 15:59:11 -07:00
Rose Thompson
167878aee4 Commet out debug code in fpga synth script. 2024-08-23 14:46:01 -07:00
Rose Thompson
b471913d9f On the way to making vcu108 work again. 2024-08-23 14:45:22 -07:00
Rose Thompson
4d56b3ca96 Maybe improvements to fpga synthesis. 2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251 More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to 
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
 2024-08-22 13:56:50 -07:00
Rose Thompson
faffecf891 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 11:02:08 -07:00
Rose Thompson
113d71f1a0 More name updates. 2024-08-21 10:51:24 -07:00
Rose Thompson
f603d21826 Updated my name in multiple locations. 2024-08-21 10:50:39 -07:00
Jacob Pease
d8b75440b6 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
baad4e0fd2 With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests. 2024-08-20 16:24:37 -05:00
Jacob Pease
43b17b5058 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
9ac889e3e8 Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose. 2024-08-20 14:40:50 -05:00
Jacob Pease
9fae5dfc0a Added dynamic SDC Clock selector in bootloader code. 2024-08-20 12:19:49 -05:00
Jacob Pease
4a1abb1d17 Added dynamic SDC Clock selector in bootloader code. 2024-08-20 12:19:49 -05:00
Jordan Carlin
4d68664e32 FPGA Makefile refactoring 2024-08-15 11:58:40 -07:00
Jordan Carlin
8ca4a5f20e
FPGA Makefile refactoring 2024-08-15 11:58:40 -07:00
Rose Thompson
375b0d0638 Merge pull request #902 from jordancarlin/build_zsbl 
Build zsbl in main Makefile
 2024-08-15 07:49:07 -07:00
Rose Thompson
e0784b2129
Merge pull request #902 from jordancarlin/build_zsbl 
Build zsbl in main Makefile
 2024-08-15 07:49:07 -07:00