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vcu108 build now starts with make vcu108 and selects the correct

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memory size, starting address, device tree location, and clock speed
for the zsbl and synthesis scripts.
This commit is contained in:
Rose Thompson 2024-09-02 14:23:16 -07:00
parent 869860bc55
commit d5e0382a81
3 changed files with 9 additions and 8 deletions
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9
fpga/generator/Makefile
View File

@ -7,20 +7,20 @@ all: ArtyA7
ArtyA7: export XILINX_PART := xc7a100tcsg324-1
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
ArtyA7: export board := ArtyA7
ArtyA7: export SYSTEMCLOCK := 20000000
ArtyA7: FPGA_Arty
ArtyA7: SYSTEMCLOCK := 20000000
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
vcu118: export board := vcu118
vcu118: export SYSTEMCLOCK := 71000000
vcu118: FPGA_VCU
vcu118: SYSTEMCLOCK := 71000000
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
vcu108: export board := vcu108
vcu108: export SYSTEMCLOCK := 50000000
vcu108: FPGA_VCU
vcu108: SYSTEMCLOCK := 50000000
# variables computed from config
EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
@ -72,7 +72,8 @@ PreProcessFiles:
# build the Zero stage boot loader (ZSBL)
.PHONE: zsbl
zsbl:
SYSTEMCLOCK = $(SYSTEMCLOCK) $(MAKE) EXT_MEM_BASE = $(EXT_MEM_BASE) EXT_MEM_RANGE = $(EXT_MEM_RANGE) -C ../zsbl
$(MAKE) -C ../zsbl clean
SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl
# Generate Individual IP Blocks
$(dst)/%.log: %.tcl

4
fpga/generator/ddr4-vcu108.tcl
View File

@ -1,7 +1,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set CPUClock $::env(CLOCK)
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
@ -39,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$SYSTEMCLOCK} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

4
fpga/generator/ddr4-vcu118.tcl
View File

@ -1,7 +1,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set CPUClock $::env(CLOCK)
set SYSTEMCLOCK $::env(CLOCK)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
@ -39,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$SYSTEMCLOCK} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \