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Author	SHA1	Message	Date
Rose Thompson	7358c1fe67	Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.	2024-11-25 15:50:29 -06:00
Rose Thompson	d311ee238c	Merge branch 'openhwgroup:main' into main	2024-11-14 16:15:26 -06:00
Rose Thompson	5e4f4c2072	Simple change to ensure Trapped instructions are included with rvvi as ... valid instructions. Required for functional coverage.	2024-11-14 16:14:02 -06:00
Rose Thompson	06fb807839	Merge pull request #1096 from davidharrishmc/dev ... XLEN32 support for functional coverage, restore WALLY-init-lib	2024-11-14 15:28:20 -06:00
Jordan Carlin	60bc968b29	Merge pull request #1097 from slmnemo/main ... Fixed oversight in assertions on verilator causing nocache_rv64gc and nodcache_rv64gc to fail	2024-11-14 12:02:37 -08:00
slmnemo	872491716d	set ZICCLSM_SUPPORTED to 0 so that nocache_rv64gc does not fail assertion tests	2024-11-14 12:00:45 -08:00
David Harris	4251f0c6a2	Restored to original WALLY-init-lib beause new flavor is moved to cvw-arch-verif and the old is needed for PMP code coverage	2024-11-14 10:56:13 -08:00
David Harris	8e6170cc83	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-11-14 08:15:44 -08:00
David Harris	054c694a27	Fixed typo of CLINT name	2024-11-14 08:14:56 -08:00
David Harris	eacc8c0f07	Define XLEN32/XLEN64 in coverage configuration	2024-11-14 08:14:22 -08:00
David Harris	669855ad25	Merge pull request #1093 from AnonymousVikram/fflag_fix ... Fflag Fix	2024-11-14 04:33:58 -08:00
Vikram Krishna	0c0949e82b	added explanation	2024-11-14 03:54:32 -08:00
Vikram Krishna	eb777d3fa4	updated froundnx conditional	2024-11-14 03:53:26 -08:00
Vikram Krishna	4aecba2a51	added handling for OpCode=100	2024-11-14 03:51:27 -08:00
Rose Thompson	88745e27d3	Fixed ila after updates.	2024-11-13 12:57:02 -06:00
David Harris	7ecd6fa991	Merge pull request #1090 from rosethompson/lrufixes ... Fixes multiple cache bugs and CacheSim.py bugs	2024-11-13 10:32:20 -08:00
Rose Thompson	a7dd2eff01	Switch rv64gc_CacheSim.py to use verilator as the default sim rather than questa.	2024-11-13 12:29:02 -06:00
Rose Thompson	e22f30ec14	Better name for CacheSetTag2.	2024-11-13 12:24:35 -06:00
Rose Thompson	db3a7d5bbd	More code cleanup for CacheSim.py	2024-11-13 10:45:33 -06:00
Jordan Carlin	b58fda89bd	Merge pull request #1088 from rosethompson/main ... Fixes lint warnings in loggers.sv updates spi device tree for vcu108	2024-11-13 08:39:32 -08:00
Rose Thompson	77d47e531f	Merge branch 'main' into lrufixes	2024-11-13 10:34:21 -06:00
David Harris	b6c69fa8a3	Merge pull request #1089 from coreyqh/dev ... Add ZicsrF coverage to fcov	2024-11-13 03:02:01 -08:00
David Harris	585a1df8c2	Merge pull request #1085 from Daniyal-R-A/Z_enable ... Enabling Bit manipulation Instructions in coverage.svh files	2024-11-13 03:01:43 -08:00
Rose Thompson	2fe73f8174	Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.	2024-11-13 00:02:51 -06:00
Rose Thompson	8993432928	Resolved issue with questa not liking the TEST +arg as a generate.	2024-11-12 23:57:30 -06:00
Corey Hickson	dcaef2080b	Add ZicsrF coverage to fcov	2024-11-12 19:09:50 -08:00
Rose Thompson	ef7072b7c2	Merge branch 'main' into lrufixes	2024-11-12 17:57:28 -06:00
Rose Thompson	5346680758	Final code cleanup.	2024-11-12 17:52:16 -06:00
Rose Thompson	b8cafb5198	More code cleanup.	2024-11-12 17:51:22 -06:00
Rose Thompson	7868af0f81	Code cleanup.	2024-11-12 17:43:09 -06:00
Rose Thompson	8659d6efdb	Resolved all CacheSim.py vs Wally mismaches.	2024-11-12 17:24:06 -06:00
Rose Thompson	d5e8ecbed5	Simplified the fpgatop SDCCLK logic.	2024-11-12 15:29:05 -06:00
Rose Thompson	f7270763a6	Merge branch 'main' of github.com:rosethompson/cvw	2024-11-12 15:06:57 -06:00
Rose Thompson	5afe634da5	Merge branch 'openhwgroup:main' into main	2024-11-12 15:05:03 -06:00
Rose Thompson	57fbd35484	Fixed lint errors in loggers.sv with Kaitlin.	2024-11-12 15:03:30 -06:00
Rose Thompson	ea2b69e1e7	Updates to wavefile.	2024-11-12 14:44:09 -06:00
Rose Thompson	383fce5522	Fixed the issue with cbo.clean.	2024-11-12 14:38:44 -06:00
Rose Thompson	b7b7c79726	CBO.FLUSH was not clearing the valid bit if the cacheline was clean.	2024-11-12 14:16:55 -06:00
Rose Thompson	5cc1fd4a85	Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.	2024-11-12 12:08:14 -06:00
Rose Thompson	8a4868ac57	Resolved a bug in the cache but there are still mismatches with the cache simulator.	2024-11-12 11:35:29 -06:00
Rose Thompson	0cf7b2e45a	Progress on fixing the cache simulator to support cbo instructions.	2024-11-11 16:37:17 -06:00
Rose Thompson	3137fd7db2	Resolved some of the issues with the cache simulator mismatching with Wally. The LRU was incorrectly updating it's state while the cache was stalled causin g the LRU state to be update when it should not be.	2024-11-11 14:23:58 -06:00
David Harris	848c5feda7	Merge pull request #1083 from jordancarlin/verilator_assertions ... Enable assertions in Verilator	2024-11-11 06:13:09 -08:00
Jordan Carlin	c776ef3fd4	enable assertions in Verilator	2024-11-10 22:20:51 -08:00
Daniyal-R-A	4107ec5b8e	Merge branch 'main' of https://github.com/openhwgroup/cvw into Z_enable	2024-11-10 20:32:45 -08:00
Daniyal-R-A	c6734e148e	Merge branch 'main' of https://github.com/openhwgroup/cvw into Z_enable	2024-11-10 20:32:08 -08:00
David Harris	f597eb8eec	Merge pull request #1081 from jordancarlin/linux_tv_gen_cleanup ... Use objcopy to fix linux testvector byte order	2024-11-10 14:59:47 -08:00
Jordan Carlin	24af6bba51	Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_tv_gen_cleanup	2024-11-09 17:38:30 -08:00
Jordan Carlin	43d0510bc7	Pad linux raw testvectors before reversing	2024-11-09 17:32:43 -08:00
Jordan Carlin	5bbaf2d95d	Remove bootmem.txt	2024-11-09 17:01:55 -08:00