Teo Ene
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e30645a4f1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-02 17:23:44 -06:00 |
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Teo Ene
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d02e22feac
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Updated coremark .do file for easier debugging
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2021-03-02 17:23:39 -06:00 |
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Noah Boorstin
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beb2beabfd
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busybear: add sim-busybear and sim-busybear-batch based on sim-wally
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2021-03-01 21:01:15 +00:00 |
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Noah Boorstin
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923489fe16
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busybear: probably discovered bug in ahb code
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2021-03-01 20:56:04 +00:00 |
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Noah Boorstin
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b6dc0a8707
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busybear: only check pc when it actually changes
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2021-03-01 19:08:35 +00:00 |
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Noah Boorstin
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b3247eadd2
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busybear: more adapting to new memory system
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2021-03-01 18:50:42 +00:00 |
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Noah Boorstin
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f11b3108d8
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busybear: fix bootram range
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2021-03-01 17:45:21 +00:00 |
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David Harris
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23a1cf63b3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-01 00:09:55 -05:00 |
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David Harris
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6f4e8b723e
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Initial (untested) implementation of lr and sc
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2021-03-01 00:09:45 -05:00 |
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Teo Ene
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2d40898158
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Properly implemented the fix from commit 5fee65231e
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2021-02-28 22:22:04 -06:00 |
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Noah Boorstin
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141f6a5496
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Merge branch 'main' into busybear
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2021-02-28 20:48:23 +00:00 |
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Noah Boorstin
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a5f1dbfe23
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add .nfs* files to gitignore
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2021-02-28 20:48:01 +00:00 |
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Noah Boorstin
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a267115635
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Merge branch 'main' into busybear
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2021-02-28 20:45:08 +00:00 |
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Noah Boorstin
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17715085ba
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busybear: start preloading bootmem
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2021-02-28 20:43:57 +00:00 |
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Noah Boorstin
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932bc0ef85
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busybear: check instead of providing InstrF
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2021-02-28 16:46:53 +00:00 |
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Noah Boorstin
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856a1079cc
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busybear: change sstatus, mstatus reset value
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2021-02-28 16:19:03 +00:00 |
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Noah Boorstin
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2769b147cb
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busybear: add 2nd dtim for bootram
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2021-02-28 16:08:54 +00:00 |
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Noah Boorstin
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969c094489
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busybear: remove gpio, start adding 2nd ram
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2021-02-28 06:02:40 +00:00 |
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Noah Boorstin
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0596d61a2a
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busybear: instantiate normal wallypipelinedsoc
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2021-02-28 06:02:21 +00:00 |
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Ross Thompson
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6191fcb1af
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Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
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2021-02-26 20:12:27 -06:00 |
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Ross Thompson
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c2cf3f9fb6
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Updating the test bench to include a function radix. Not done.
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2021-02-26 19:43:40 -06:00 |
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David Harris
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73920282af
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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David Harris
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0258901865
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Cleaned out unused signals
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2021-02-26 09:17:36 -05:00 |
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kaveh pezeshki
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e8b306bcba
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merged with main to integrate with AHB
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2021-02-26 05:37:10 -08:00 |
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Noah Boorstin
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4c7b185d90
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busybear: add main ram loading, better instr checking also
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2021-02-26 20:26:54 +00:00 |
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kaveh Pezeshki
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2782ca2480
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fixed sensitivity list on error checking always block, removed useless once and for all
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2021-02-26 13:41:16 -05:00 |
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kaveh pezeshki
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adadc21fc6
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restored
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2021-02-26 02:22:08 -08:00 |
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David Harris
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225102047a
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Clean up bus interface code
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2021-02-26 01:03:47 -05:00 |
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David Harris
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1b61d78ac2
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Retimed peripherals for AHB interface
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2021-02-26 00:55:41 -05:00 |
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Brett Mathis
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87e4311339
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Fcmp/Fsgn pipeline modules
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2021-02-25 18:22:30 -06:00 |
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David Harris
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bad180fc15
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-02-25 15:49:38 -05:00 |
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David Harris
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f57096a5d2
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Restored to working multiplier after Lab 2
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2021-02-25 15:32:43 -05:00 |
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Brett Mathis
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b0a5052bcf
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FPU Assembly tests
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2021-02-25 14:32:36 -06:00 |
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Teo Ene
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a35fdac75b
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Fixed previous commit
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2021-02-25 11:24:44 -06:00 |
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Teo Ene
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5fee65231e
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Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.
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2021-02-25 11:23:01 -06:00 |
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Teo Ene
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b9701293a0
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Changed TIMBASE in coremark config file
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2021-02-25 11:03:41 -06:00 |
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Teo Ene
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a6c16af721
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Merge remote-tracking branch 'origin/lab3' into main
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2021-02-25 10:28:20 -06:00 |
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Teo Ene
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8491deb1a9
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Changed .do file back to run all
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2021-02-25 09:58:54 -06:00 |
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David Harris
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cd4ba8831c
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Merged bus into main
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2021-02-25 00:28:41 -05:00 |
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David Harris
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eb52fd1c5a
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removed WALLY ALU tests to avoid merge conflict with main branch
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2021-02-25 00:15:22 -05:00 |
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Teo Ene
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cfd45a46c3
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Added provisional coremark files from work with Elizabeth
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2021-02-24 20:07:07 -06:00 |
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kaveh pezeshki
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251aa982eb
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condensed always blocks to avoid race conditions
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2021-02-24 11:35:28 -08:00 |
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Noah Boorstin
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ddaf67c043
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busybear: preload bootram
thanks to Prof Stine for the .do file commands
@kaveh can you check line 201? it does nothing, but things break when
I remove that line
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2021-02-24 18:46:09 +00:00 |
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David Harris
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38b8cc652c
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All tests passing with bus interface
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2021-02-24 07:25:03 -05:00 |
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kaveh pezeshki
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06f73fe5fe
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added comments for RAM and bootram, removed trailing whitepace
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2021-02-23 21:28:33 -08:00 |
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Noah Boorstin
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b7f4e72eec
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busybear: add bootram section in the same manner as ram
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2021-02-24 02:02:28 +00:00 |
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Noah Boorstin
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914a36e3e8
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busybear: add support for subwords in ram
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
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2021-02-24 01:51:18 +00:00 |
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Noah Boorstin
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7b7e87bd0b
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busybear: start adding ram
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2021-02-23 22:01:23 +00:00 |
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Katherine Parry
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07641203ee
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-02-23 20:21:53 +00:00 |
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Katherine Parry
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906ec30339
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inital FMA push
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2021-02-23 20:19:12 +00:00 |
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